Fault diagnosis of compressed test responses

A computer-implemented method of diagnosing faults in a circuit-under-test comprising:

• receiving an error signature comprising multiple bits, the bits of the error signature corresponding to bits of a compressed test response produced by a compactor in the circuit-under-test, the bits of the error signature further comprising one or more error bits that indicate errors at corresponding bit locations of the compressed test response;
• selecting at least one error bit of the error signature;
• selecting at least one scan cell candidate from a set of scan cells known to contribute to the bit of the compressed test response corresponding to the selected at least one error bit;
• and
• determining whether the selected at least one scan cell candidate explains the selected at least one error bit in the error signature by updating the error signature to include the contribution of the at least one selected error bit.

A computer-implemented method of diagnosing faults in a circuit-under-test, comprising:

• receiving at least first and second error signatures, each error signature comprising error bits that indicate the presence of one or more errors in one or more corresponding compressed test responses produced by a compactor on the circuit-under-test in response to at least one applied test pattern, the first error signature further comprising one or more unknown bits;
• generating a search tree that identifies one or more sets of scan cells that explain the error bits in the first error signature;
• and
• determining whether any of the identified one or more sets of scan cells also explain the error bits of a second signature, the second signature being different from the first signature.