Method and system for reducing pin count in an integrated circuit when interfacing to a memory
AssigneeLSI Corporation
InventorsGordon Charles, Emanuel Washington
Life of this patent
Estimating the term…
Abstract
The invention provides a system and method for reducing pin count in an integrated circuit (IC) when interfacing to a synchronous dynamic random access memory (SDRAM). The SDRAM has a plurality of address lines and a plurality of data lines. The method includes connecting together the plurality of data lines and the plurality of address lines. The IC interfaces to the SDRAM through the connected plurality of address lines and the plurality of data lines.
Claims34
A method for reducing pin count in an integrated circuit (IC) when interfacing with a synchronous dynamic random access memory (SDRAM) having a plurality of address lines and a plurality of data lines, comprising:
- connecting together the plurality of data lines and the plurality of address lines;
- and
- interfacing the IC to the SDRAM through the connected plurality of address lines and the plurality of data lines.
A method for writing to a de facto synchronous dynamic random access memory (SDRAM) having a plurality of address lines and a plurality of data lines, wherein the plurality of data lines and the plurality of address lines are connected together, from an integrated circuit (IC), comprising;
- transmitting a write command from the IC to the SDRAM in order to initiate a write operation;
- and
- transmitting an address for writing data along the connected plurality of address lines and the plurality of data lines.
A method for reading from a synchronous dynamic random access memory (SDRAM) having a plurality of address lines and a plurality of data lines, wherein the plurality of data lines and the plurality of address lines are connected together, from an integrated circuit (IC), comprising;
- transmitting a read command from the IC to the SDRAM in order to initiate a read operation;
- and
- transmitting an address for reading data along the connected plurality of address lines and the plurality of data lines.
A system for reducing pin count in an integrated circuit (IC) when interfacing with a synchronous dynamic random access memory (SDRAM), comprising;
- a plurality of address pins;
- a plurality of data pins;
- and
- a memory controller coupled to the plurality of address pins and the plurality of data pins and configured to transmit data signals and address signals to one of the plurality of data pins and the plurality of address pins.
Dependencies are inferred from the claim text.