US 2006/0041705 A1 · SYSTEM AND METHOD FOR ARBITRATION BETWEEN SHARED PERIPHERAL CORE DEVICES IN SYSTEM ON CHIP ARCHITECTURES

Abstract

A system for implementing arbitration between one or more shared peripheral core devices in system on chip (SOC) integrated circuit architecture includes a first microprocessor in communication with a first system bus, and a second microprocessor in communication with a second system bus. At least one peripheral core device is accessible by both the first microprocessor and said second microprocessor, and an arbitration unit is in communication with the first system bus and the second system bus. The arbitration unit is configured to control communication between the at least one peripheral core device and the first and second microprocessors.

Claims20

Dependent claims

A system for implementing arbitration between one or more shared peripheral core devices in a system on chip (SOC) integrated circuit architecture, comprising:

a first microprocessor in communication with a first system bus;
a second microprocessor in communication with a second system bus;
at least one peripheral core device accessible by both said first microprocessor and said second microprocessor;
and
an arbitration unit in communication with said first system bus and said second system bus;
wherein said arbitration unit is configured to control communication between said at least one peripheral core device and said first and second microprocessors.

3 more elements

A method for implementing arbitration between one or more shared peripheral core devices in a system on chip (SOC) integrated circuit architecture, the method comprising:

configuring a first microprocessor in communication with a first system bus;
configuring a second microprocessor in communication with a second system bus;
configuring at least one peripheral core device to be accessible by both said first microprocessor and said second microprocessor;
and
configuring an arbitration unit in communication with said first system bus and said second system bus, wherein said arbitration unit controls communication between said at least one peripheral core device and said first and second microprocessors.

2 more elements

Dependencies are inferred from the claim text.

System and method for arbitration between shared peripheral core devices in system on chip architectures

Life of this patent

System and method for arbitration between shared peripheral core devices in system on chip architectures

Life of this patent

Abstract

Claims20