US 2006/0041692 A1Published application

Data processing appratus with address redirection in response to periodic address patterns

OwnerBijo Thomasinventor

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Abstract

A processing system comprises a detection unit which detects repetitions of periods of access address patterns output from at least one of a plurality of processing units. The interface switches selectable connections between the data input and/or outputs of the processing units and the data input and/or outputs of selectable ones of a plurality of memory units. As a result a same addresses from at least one of the plurality of processing units alternately addresses a location in different ones of the memory units in dependence on the detection of said repetition. Preferably, the detection unit contains an address comparator arranged to detect whether addresses from the address output of a first one of the data processing units fall in a range of one or more addresses associated with the memory units. The detector generates a detection signal indicating the new one of said repetitions each time when one of the addresses from the address output of the first one of the data processing units has output addresses in said range a certain number of times.

Claims11

Dependent claims

A data processing apparatus, comprising:

a plurality of data processing units (l0a-b), each having an address output (14, 15) and a data input and/or output (12, 13);
a plurality of memory units (18a,b), each having an address input and a data input and/or output;
a switching unit (16, 17) comprising:
first selectable connections between the data input and/or outputs (12, 13) of the processing units (10a) and selectable ones of the data input and/or outputs of the memory units (18a,b),
second selectable connections from the address outputs of the processing units (10b) to the address inputs of selectable ones of the memory units (18a,b),
a detection unit (20a, 30, 32) coupled to the address outputs of the processing units (10a,b), arranged to detect repetitions of a period of an address pattern output by the at least one of the processing units (10a,b),
a state holding element (22a, 34) for controlling the first and second selectable connections, the state holding element (22a, 34) having an input coupled to the detection unit (20a, 30, 32), in order to switch the first and second selectable connections in response to the detection of a new one of said repetitions, so that identical addresses from the data processing units (10a,b) alternately map to different ones of the memory units (18a,b) during successive repetitions.

4 more elements

Dependencies are inferred from the claim text.