US 2006/0040462 A1 · Novel method to improve SRAM performance and stability

Abstract

A technique is disclosed for increasing the width of a transistor (300) while the transistor itself may be scaled down. The transistor width (382) is increased by forming recesses (352) within shallow trench isolation (STI) regions (328) adjacent to the transistor (300). The recesses (352) provide an area that wraps around the transistor and thereby increases the width (382) of the transistor (300). This wraparound area provides additional space for dopant atom deposition, which facilitates a reduction in random dopant fluctuation (RDF). In this manner, transistors formed in accordance with one or more aspects of the present invention, may yield improved performance when incorporated into SRAM since the probability that such transistors will be more closely matched is increased.

Claims20

Dependent claims

A method of forming shallow trench isolation (STI) regions so that a transistor formed there-between has an increased width, comprising:

over etching the entire upper surface of STI structures formed within inactive regions of a substrate to establish respective STI recesses with the STI structures;
and
forming one or more layers of transistor building materials within the STI recesses and over an active region of the substrate, the active region of the substrate located between the STI structures, where forming the transistor building materials within the recesses increases the width of the transistor.

A method of forming at least some of a transistor between shallow trench isolation (STI) regions that are formed to allow the transistor to have an increased width, comprising:

forming a layer of thin oxide material over a substrate;
forming a layer of nitride material over the layer of oxide material;
forming an first layer of masking material over a substrate or one or more layers overlying the substrate;
patterning the first layer of masking material over inactive regions within the substrate;
patterning the substrate as well as layers overlying the substrate to form STI cavities with the patterned first layer of masking material serving as a guide;
removing the patterned first layer of masking material;
filling the STI cavities with an insulating material;
removing excess STI insulating material to establish STI structures;
forming a second layer of masking material over the STI structures and the substrate or one or more layers overlying the substrate;
patterning the second layer of masking material;
removing the one or more layers overlying the substrate and the entire upper surface of some of the STI structures to establish respective STI recesses within the STI structures;
removing the patterned second layer of masking material;
forming one or more layers of transistor building materials within the STI recesses and over an active region of the substrate, the active region of the substrate located between the STI structures, where the transistor building materials formed within the recesses increases the width of the transistor.

10 more elements

A method of forming shallow trench isolation (STI) regions so that a transistor formed there-between has an increased effective width, comprising:

forming a layer of thin oxide material over a substrate;
forming a layer of nitride material over the layer of oxide material;
forming an STI layer of masking material over the nitride layer;
patterning the STI layer of masking material over inactive regions within the substrate;
patterning the layer of nitride material, layer of thin oxide material, and substrate to form STI cavities with the patterned STI layer of masking material serving as a guide;
removing the patterned STI layer of masking material;
filling the STI cavities with an insulating material;
removing excess STI insulating material and some of the layer of nitride material to establish STI structures;
removing the remainder of the layer of nitride material;
forming a layer of VtADJUST masking material over the STI structures and the layer of thin oxide material;
paterning the layer of VtADJUST masking material;
performing a VtADJUST implant;
removing the layer of thin oxide material and some of the STI structures to establish respective STI recesses within the STI structures;
forming a thin layer of sacrificial oxide material over the surface of the substrate and STI structures;
removing the layer of sacrificial oxide material;
removing the patterned VtADJUST masking material;
forming a thin layer of gate dielectric material over the substrate and STI structures;
and
forming a layer of gate electrode material over the layer of gate dielectric material.

16 more elements

Dependencies are inferred from the claim text.

Novel method to improve SRAM performance and stability

Life of this patent

Novel method to improve SRAM performance and stability

Life of this patent

Abstract

Claims20