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US 2006/0040460 A1Published application
MIS capacitor and production method of MIS capacitor
AssigneeFujitsu Limited
InventorsYasushi Kakimura, Keisuke Muraya
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Abstract
Silicon wafer, with diffusion area formed in a predetermined area of one side, consists of the lower electrode of capacitor. The first metal layer is connected to the first power supply wiring VDD and consists of the upper electrode of capacitor. The second metal layers are connected to the second power supply wiring GND and are formed on the side where diffusion area is formed on silicon wafer. Oxide film is placed between the first metal layer and the surface of silicon wafer where the diffusion area is formed.
Claims8
A MIS capacitor comprising:
- silicon wafer that is with diffusion area formed in a predetermined area of one side and that comprises the lower electrode of the capacitor;
- a first metal layer that is connected to a first power supply wiring and that comprises the upper electrode of the capacitor;
- a second metal layer connected to a second power supply wiring and formed on the surface of the diffusion area of the silicon wafer;
- and
- an oxide film placed between the first metal layer and the surface of the diffusion area on the silicon wafer.
2 more elements
A MIS capacitor production method, comprising:
- forming diffusion area on a predetermined area of a silicon wafer;
- forming a insulator layer on the silicon wafer;
- making a first hole, a second hole, and a third hole on the insulator layer, each of the holes reaches the diffusion area on the silicon wafer through the insulator layer;
- forming oxide film with a predetermined thickness at the bottom of the first hole;
- and
- filling the first hole, the second hole, and the third hole with metal.
3 more elements
Dependencies are inferred from the claim text.