SONET/SDH SPE/virtual container retiming with adaptive dual pointer leak rate computation

An apparatus for retiming and realigning SONET signals, comprising:

• a) a dual port RAM FIFO;
• b) a write address generator based on an incoming signal clock;
• c) a read address generator based on an outgoing signal clock;
• d) a FIFO depth counter synchronized to First_Byte of an SPE written to the FIFO;
• e) a FIFO depth latch synchronized to First_Byte read from the FIFO;
• f) means for indicating a calculated slow leak rate when the FIFO depth is more than a first threshold and less than a second threshold from half full;
• and
• g) means for indicating a calculated fast leak rate when the FIFO depth is more than a second threshold and less than a third threshold from half full.

An apparatus for retiming and realigning SONET signals, comprising:

• a) a dual port RAM FIFO;
• b) a write address generator based on an incoming signal clock;
• c) a read address generator based on an outgoing signal clock;
• d) a FIFO depth counter synchronized to First_Byte of an SPE written to the FIFO;
• e) a FIFO depth latch synchronized to First_Byte read from the FIFO;
• f) a logic element indicating a calculated slow leak rate when the FIFO depth is more than a first threshold and less than a second threshold from half full and a calculated fast leak rate when the FIFO depth is more than a second threshold and less than a third threshold from half full.