SONET/SDH frame synchronization in the presence of high bit error rates

An apparatus for frame synchronization of an STS-N (Synchronous Transport Signal—N) having N A1 bytes, including a first A1 byte and a last A1 byte, and N A2 bytes, including a first A2 byte and a last A2 byte, where N is an integer greater than or equal to 3, comprising:

• a plurality of shift registers having the same bit depth, the number of shift registers being equal to the bit depth, each shift register having an input and an output, each shift register having a phase offset of one bit relative to a next shift register;
• a plurality of frame detectors, one coupled to each shift register, each phase detector having an output;
• a multiplexer having a plurality of data inputs, a select input, and an output, the output of each shift register being coupled to a data input of the multiplexer;
• and
• selector circuitry having an input coupled to the outputs of the frame detectors and an output coupled to the select input of the multiplexer, wherein each frame detector detects a framing pattern having twenty-four bits and signals the selector circuitry when the framing pattern has been detected, and
• the twenty-four bits are selected form the group consisting of the first and last A1 bytes plus the first A2 byte, the first and last A1 bytes plus the last A2 byte, the first and last A2 bytes plus first A1 byte, and the first and last A2 bytes plus last A1 byte.