Memory device having staggered memory operations

A method of reading a set of data from an integrated-circuit memory, the method comprising:

• a. receiving a read request for the set of data;
• b. activating, in response to the read request, a first sub-bank containing a first subset of the data;
• c. activating, in response to the read request, a second sub-bank containing a second subset of the data;
• d. reading, after activating the second sub-bank, the first sub-bank to obtain the first subset of data;
• e. reading the second sub-bank to obtain the second subset of data;
• and
• f. combining the first and second subsets of data into a serial data word.

A method of writing a set of data to an integrated-circuit memory, the method comprising:

• a. receiving a write request;
• b. receiving the set of data;
• c. dividing the set of data into first and second parallel data words;
• d. activating, in response to the write request, a first sub-bank;
• e. activating, after activating the first sub-bank and in response to the write request, a second sub-bank;
• f. writing the first parallel data word to the first sub-bank;
• and
• g. writing, after writing the first parallel data word to the first sub-bank, the second parallel data word to the second sub-bank.

A memory system comprising:

• a. a request interface adapted to receive memory requests;
• b. bank-access control circuitry coupled to the request interface, the bank-access control circuitry including:
• i. a decoder coupled to the request interface and adapted to decode the memory requests;
• ii. activation logic coupled to the decoder and adapted to issue first and second activation commands via respective first and second activation ports;
• c. a first sub-bank including:
• i. a first plurality of memory cells;
• ii. a first plurality of data lines coupled to the memory cells;
• and
• iii. a first memory control port coupled to the first activation port;
• iv. wherein the first sub-bank activates the first plurality of memory cells in response to the first activation command;
• and
• d. a second sub-bank including:
• i. a second plurality of memory cells;
• ii. a second plurality of data lines coupled to the memory cells;
• and
• iii. a second memory control port coupled to the second activation port;
• iv. wherein the second sub-bank activates the second plurality of memory cells in response to the second activation command.

A memory module comprising:

• a. a plurality of logical memory banks, each logical memory bank divided into a corresponding plurality of sub-banks, including a first sub-bank having a first plurality of data lines and a second sub-bank having a second plurality of data lines;
• b. a request interface adapted to receive operation requests directed to the logical memory banks;
• and
• c. bank-access control logic coupled to the request interface and adapted to receive and decode the operation requests, the bank access control logic including a first control port coupled to a first sub-bank and a second control port coupled to the second sub-bank, the bank-access control logic issuing, in response to one of the operation requests, a first activate command to the first sub-bank on a first clock cycle and a second activate command to the second sub-bank on a second clock cycle.

A memory circuit comprising:

• a. a plurality of logical memory banks, each logical memory bank divided into a corresponding plurality of sub-banks, including a first sub-bank and a second sub-bank;
• b. means for sequentially activating, in response to a memory request directed to one of the logical memory banks, the first sub-bank and the second sub-bank;
• and
• c. means for sequentially accessing, in response to the memory request, the first sub-bank and the second sub-bank.