Power efficient read circuit for a serial output memory device and method

4:

• The memory device of claim 2 wherein each of said memory cells is a split gate floating gate non-volatile memory cell having a first region in a semiconductor substrate, a second region in said semiconductor substrate spaced apart from said first region by a channel region;
• a floating gate for controlling the conduction of current in a first portion of said channel region;
• a control gate for controlling the conduction of current in a second portion of said channel region;
• wherein said control gate is separated from said floating gate by an insulator permitting the Fowler Nordheim tunneling of electrons from said floating gate to said control gate.

6:

• A method of managing power in a memory device having a plurality of memory cells arranged in a plurality (k) of arrays, each array having a plurality of rows, and one or more column lines, and a plurality of row lines connecting to the memory cells in each array, wherein each memory cell in an array is addressable by a column line and a row line, a plurality (k) of sense amplifiers, one sense amplifier associated with each array, connectable to one or more column lines of said array and for receiving a signal therefrom supplied from an addressed memory cell;
• a register;
• and a control circuit for receiving a read command, and a clock signal, and in response to the read command for controlling said plurality of sense amplifiers and said register;
• said method comprising:
• determining a time period sufficient to sense the signal on a connected column line associated with each of a first plurality (j) of said plurality (k) of sense amplifiers (j<k);
• activating said first plurality (j) of sense amplifiers for said time period;
• latching the signal into said register;
• deactivating said first plurality (j) of sense amplifiers;
• and
• serially outputting the signal from said register in response to said clock signal.