Self-adaptive program delay circuitry for programmable memories
AssigneeAtmel Corporation
InventorsMarylene Combe, Jean-Michel Daga
Life of this patent
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Abstract
A self-adaptive programming circuit for EEPROM is used to automatically tune an erase or write delay, providing an improved programming window. The programming circuit may also provide improvements in data retention for programmed memory cells. The invention can be applied more particularly in the field of EEPROM memories capable of page mode writing operations.
Claims29
A method to improve data retention in an array of programmable memory cells comprising:
- defining a margin reference voltage that is different than a normal memory cell read voltage;
- reading a logic value content of at least one memory cell;
- using said margin reference voltage as a reference for comparison with said logic value content;
- comparing said logic value content of the at least one memory cell automatically to an expected logic value;
- and
- adjusting a programming parameter automatically if said memory cell logic value content is different than said expected logic value.
A machine readable medium having stored therein instructions for use in a machine to improve data retention in an array of programmable memory cells, the instructions comprising:
- instructions to define a margin reference voltage that is different than a normal memory cell read voltage;
- instructions to read a logic value content of at least one memory cell;
- instructions to use said margin reference voltage as a reference for comparison with said logic value content;
- instructions to compare said logic value content of the at least one memory cell automatically to an expected logic value;
- and
- instructions to adjust a programming parameter automatically if said memory cell logic value content is different than said expected logic value.
A programmable memory circuit comprising:
- an array of memory cells, said memory cells capable of storing at least one logic value;
- an address circuit coupled to said array of memory cells, said address circuitry capable of selecting at least one memory cell;
- at least one voltage reference generator coupled to said array of memory cells, said generator capable of providing a range of voltages;
- a plurality of latch circuits coupled to said array of memory cells, said latch circuit capable of storing at least one expected logic value and at least one state latch;
- a sense circuit coupled to said at least one memory cell;
- at least one comparator coupled to said sense circuitry;
- and
- a sequencer defining an address value used by said address circuit, the sequencer configured to define a margin reference voltage.
Dependencies are inferred from the claim text.