Non-volatile memory cell, fabrication method and operating method thereof

A non-volatile memory, comprising:

• a memory cell array, wherein each column of the memory cell array includes a plurality of first memory cells and a plurality of second memory cells;
• a plurality of selecting units, each disposed on one side of each column of the memory cell array respectively, wherein in each column the selecting unit and the plurality of first memory cells are arranged to form a plurality of gaps and each of the plurality of second memory cells stuffs up a different one of the gaps respectively;
• a plurality of first doped regions, each disposed on the other side of each column of the memory cell array respectively;
• a plurality of second doped regions, each disposed adjacent to each of the plurality of selecting units respectively;
• a plurality of word lines;
• a plurality of bit lines, wherein each intersection of the plurality of word lines and each of the plurality of bit lines is corresponding to a different one of the plurality of first memory cells or the plurality of second memory cells;
• a plurality of selecting lines, each connected to a different row of the plurality of selecting units;
• and
• a plurality of common lines, each connected to a different row of the plurality of first doped regions.

A non-volatile memory unit, comprising:

• a first memory cell disposed on a substrate;
• a selecting unit, disposed on the substrate and separated from the first memory cell by a gap;
• a second memory cell stuffed into the gap;
• a first insulation spacer, separating the first memory cell and the second memory cell;
• and
• a second insulation spacer, separating the selecting unit and the second memory cell;
• wherein the first memory cell comprises a first gate, the second memory cell comprises a second gate and the selecting unit comprises a third gate for turning on/off channel regions thereunder.

An operating method for a non-volatile memory, the memory comprising:

• a memory cell array with each column including a plurality of first memory cells and a plurality of second memory cells;
• a plurality of selecting units, each disposed on one side of each column of the memory cell array respectively, wherein in each column the selecting unit and the plurality of first memory cells are arranged to form a plurality of gaps and each of the plurality of second memory cells stuffs up a different one of the gaps respectively;
• a plurality of source regions, each disposed on the other side of each column of the memory cell array respectively;
• a plurality of drain regions, each disposed adjacent to each of the plurality of selecting units respectively;
• a plurality of word lines;
• a plurality of bit lines, wherein each intersection of the plurality of word lines and each of the plurality of bit lines is corresponding to a different one of the plurality of first memory cells or the plurality of second memory cells;
• a plurality of selecting lines, each connected to a different row of the plurality of selecting units;
• and a plurality of common lines, each connected to a different row of the plurality of source regions;
• the method comprising:
• while programming a selected memory cell, applying 0V to a selected bit line and applying a first voltage to unselected bit lines, applying a second voltage to a selected word line near a word line coupled to the selected memory cell and adjacent to the drain region, applying a third voltage to unselected word lines and the selecting line, and applying a fourth voltage to a source line to program the selected memory source by source-side injection method.

A method of fabricating a non-volatile memory, comprising:

• providing a substrate;
• forming a plurality of gate structures over the substrate, each of the gate structures comprising a first composite dielectric layer, a first gate, and a cap layer, wherein every two of the plurality of gate structures are separated by a gap;
• forming insulation spacers on sidewalls of the gate structures;
• forming a second composite dielectric layer over the substrate;
• forming a conductive layer over the substrate;
• removing a portion of the conductive layer to form a plurality of second gates in the gaps between the gate structures, the second gates and the gate structures constituting a memory cell column;
• and
• forming a source region and a drain region in the substrate respectively adjacent to two sides of the memory cell column.