Method for reading uniform channel program (UCP) flash memory cells
AssigneeInfineon Technologies AG
InventorsAchim Gratz, Mayk Roehrich, Klaus Knobloch
Life of this patent
Estimating the term…
Abstract
A flash memory cell can be read by selecting a local bit line. A read potential is applied to a memory cell transistor associated with the local bit line thereby generating a capacitive loading of the local bit line. The capacitive loading depends upon a magnitude of charge stored on a floating gate of the memory cell transistor. The capacitive loading of the local bit line can then be assessed to determine a state of the memory cell transistor, the state being related to the magnitude of the charge stored on the floating gate.
Claims20
A method for reading a flash memory cell, the method comprising:
- selecting a bit line;
- applying a read potential to a memory cell transistor associated with the bit line thereby generating a capacitive loading of the bit line, the capacitive loading being dependent upon a magnitude of charge stored on a floating gate of the memory cell transistor;
- and
- assessing the capacitive loading of the bit line to determine a state of the memory cell transistor, the state being related to the magnitude of the charge stored on the floating gate.
A method for the read-out of a UCP (Uniform Channel Program) flash memory cell, the method comprising:
- selecting a local bit line by means of a respective select signal on a respective sector select line by virtue of the respective local bit line switching to a respective global bit line via a respective sector select selection transistor, the sector select selection transistor including a gate that is connected to a sector select line, wherein the selected local bit line includes a memory cell transistor that is driven by a respective read potential via a word line and that is associated with a bit column, wherein the bit column comprises memory cell transistors respectively connected in parallel in pairs by drain and source terminals, the drain terminals being connected via the local bit line and the source terminals not being connected to a fixed potential;
- and
- performing a read-out operation by a procedure whereby a capacitive loading of the local bit line dependent on a magnitude of charge stored on a floating gate of the driven memory cell transistor is generated, a read-out signal being provided on the local bit line and being dependent on a magnitude of the capacitive loading of the local bit line, wherein the read-out signal is assessed by a read block connected to the local bit line, the read block determining a LOW or HIGH level of a bit signal that corresponds to a bit occupancy of the memory cell transistor, the bit occupancy being represented by the magnitude of the charge stored on the floating gate.
A memory device comprising:
- a plurality of memory cell transistor pairs, each memory cell transistor pair comprising a first memory cell transistor having a source and a drain and a second memory cell transistor having a source and a drain, wherein the sources of the first and second memory cell transistors of each pair are coupled together at a common source region;
- a bit line coupled to the drains of the first and second memory cell transistors of each memory cell transistor pair;
- a ground line coupled to bodies of the first and second memory cell transistors of each memory cell transistor pair such that a capacitance exists between the ground line and the common source region of each memory cell transistor pair;
- and
- a plurality of word lines, each word line being coupled to a respective gate of one of the first or second memory cell transistors.
Dependencies are inferred from the claim text.