An esd protection power clamp for suppressing esd events occurring on power supply terminals

An ESD protection power clamp for suppressing ESD events comprising:

• an FET transistor having drain and source connections connected across power supply terminals of an integrated circuit for clamping the voltage at said terminals during and ESD event;
• an RC timing circuit connected between the power supply terminals which provide a voltage proportional to an ESD voltage for triggering said FET transistor out of conduction following an ESD event;
• an inverter circuit comprising first, second and third stages of pull-up and pull-down transistors connected in tandem, a first stage of said inverter connected to said RC timing circuit, and a third stage of said inverter circuit providing an output for said inverter connected to said FET gate connection;
• and
• a feedback transistor connected in series with said second stage pull up transistor, and having a gate connection connected to said FET transistor gate connection, wherein during a power event where normal power supply voltage is applied to said power supply terminals, said feedback transistor prevents said FET transistor from latching into a clamping mode.

An ESD protection power clamp for suppressing ESD events comprising:

• an FET transistor having drain and source connections connected across power supply terminals of an integrated circuit, and a gate connection;
• an RC timing circuit connected between the power supply terminals which provide a voltage proportional to an ESD voltage for triggering said FET transistor into connection;
• an inverter circuit comprising first and second stages of pull-up and pull-down transistors connected in tandem, a first stage of said inverter connected to said RC timing circuit, and a second stage of said inverter circuit providing an output for said inverter connected to said FET gate connection;
• and
• a first feedback transistor having a gate connected to said gate connection of said FET transistor and having a source and drain connected in series with a pull-up transistor of said first stage for preventing said FET transistor from latching into a clamping mode;
• and
• a second feedback transistor having source and drain connections connected across said serial connection of said first transistor and said pull-up transistor, said second feedback transistor reducing power consumption during a power up of said power supply voltage.