Very linear wide-range pipelined charge-to-digital converter

A method for analog to digital conversion using a multichannel analog to digital conversion circuit and wherein the multichannel analog to digital conversion circuit includes a plurality of linearized channels wherein each channel comprises a multi-stage pipelined charge-to-digital converter and an integrating capacitor within each stage of the four-stage converter, the integrating capacitor storing a charge proportional to an integral of an input charge, the method comprising:

• disconnecting input to a first stage of the multi-stage converter during subsequent stage sampling of an output from the first stage;
• presampling the output from the first stage in subsequent stages;
• disabling of charge removal in the first stage during subsequent stage sampling to avoid sample corruption;
• limiting discharge-current within respective stages using a discharge-current limiter;
• bypassing of the discharge-current limiter at timed intervals to insure all sampled charge is counted by end of each respective integration period;
• disabling of charge removal in a present-stage when bypassing in that stage;
• opening of present-stage bypass and/or discharge switches when sampling by subsequent stages;
• and,
• disabling of present-stage charge removal prior to and during subsequent stage sampling.

A multi-channel analog to digital conversion circuit comprising:

• a plurality of channels, wherein each channel comprises a multi-stage pipelined charge-to-digital converter and an integrating capacitor within each stage of the multi-stage converter, the integrating capacitor storing a charge proportional to an integral of an input charge and wherein each stage of the respective linearized channels is configured for calculating gain and offset for each stage in the channel to be used in subsequent integration periods;
• wherein each of the multi-stage pipelined charge-to-digital converter comprises at least one stage current-processing integrate and fold amplifier stage coupled in series with a plurality of subsequent voltage-processing integrate and fold amplifier stages;
• and,
• each of the integrate and fold amplifier stages comprises:
• an amplifier having an input voltage and output voltage, an inverting terminal connected to the input voltage;
• the integrating capacitor connected between the inverting capacitor connected between the inverting terminal and an output terminal of the amplifier;
• and,
• a charge subtracting circuit selectively coupled to the inverting terminal and wherein the charge subtracting circuit is configured for removing a respective predetermined charge a number of times from the integrator capacitor.