Digital lock detector for PLL

A method for detecting that an output clock is locked to a reference clock, said method comprising:

• receiving said reference clock;
• frequency dividing said reference clock by a factor N to produce a frequency-divided clock;
• receiving said output clock;
• counting a number M of clock edges of said output clock during a time interval of said frequency divided clock, wherein said output clock is frequency-locked to said reference clock when said number M satisfies a predetermined relationship to said factor N;
• detecting whether said reference clock leads or lags said output clock;
• detecting whether said reference clock leads or lags a delayed version of said output clock, wherein said output clock is phase-locked to said reference clock when said reference clock lags said output clock and leads said delayed output clock;
• and
• outputting a signal indicating that said output clock is frequency-locked and phase-locked to said reference clock.

A circuit for detecting that an output clock is locked to a reference clock, said circuit comprising:

• a frequency divider operative to receive said reference clock as input, and to frequency divide said reference clock by a factor N in order to produce a frequency-divided clock;
• a counter operative to receive said output clock as input, and to count a number M of clock edges of said output clock during a time interval of said frequency-divided clock, wherein said output clock is frequency-locked to said reference clock when said number M satisfies a predetermined relationship to said factor N;
• and
• a phase sampler operative to:
• receive as input and compare phases of said output clock, a delayed version of said output clock and said reference clock, wherein said output clock is phase-locked to said reference clock when said phase of said reference clock is between said phases of said output clock and said delayed output clock;
• and
• output a signal indicating that said output clock is frequency-locked and phase-locked to said reference clock.

A circuit for detecting that an output clock is locked to a reference clock, said method comprising:

• a frequency divider operative to receive said reference clock as input, and to frequency divide said reference clock by a factor N in order to produce a frequency-divided clock;
• a counter operative to receive said output clock as input, and to count a number M of clock edges of said output clock during a time interval of said frequency-divided clock, wherein said output clock is frequency-locked to said reference clock when said number M satisfies a predetermined relationship to said factor N;
• a first flip-flop operative to receive said output clock and said reference clock, and to detect whether said reference clock leads or lags said output clock;
• a second flip-flop operative to receive a delayed version of said output clock and said reference clock, and to detect whether said reference clock leads or lags said delayed version of said output clock, wherein said output clock is phase-locked to said reference clock when said reference clock lags said output clock and leads said delayed output clock;
• and
• a third flip-flop operative to receive a first signal indicating whether said output clock is frequency-locked to said reference clock and a second signal indicating whether said output clock is phase-locked to said output clock as input, and to output a signal indicating that said output clock is frequency-locked and phase-locked to said reference clock.

Apparatus for detecting that an output clock is locked to a reference clock, said apparatus comprising:

• means for receiving said reference clock;
• means for frequency dividing said reference clock by a factor N to produce a frequency-divided clock;
• means for receiving said output clock;
• means for counting a number M of clock edges of said output clock during a time interval of said frequency-divided clock, wherein said output clock is frequency-locked to said reference clock when said number M satisfies a predetermined relationship to said factor N;
• means for comparing phases of said output clock, a delayed version of said output clock and said reference clock, wherein said output clock is phase-locked to said reference clock when said phase of said reference clock is between said phases of said output clock and said delayed output clock;
• and
• means for outputting a signal indicating that said output clock is frequency-locked and phase-locked to said reference clock.

A computer system comprising:

• a processor;
• a memory controller coupled to said processor;
• a plurality of dynamic random access memory (DRAM) chips coupled to said memory controller, at least one of said DRAM chips comprising at least one circuit for detecting that an output clock is locked to a reference clock, said at least one circuit comprising:
• circuitry for receiving said reference clock;
• circuitry for frequency dividing said reference clock by a factor N to produce a frequency-divided clock;
• circuitry for receiving said output clock;
• circuitry for counting a number M of clock edges of said output clock during a time interval of said frequency-divided clock, wherein said output clock is frequency-locked to said reference clock when said number M satisfies a predetermined relationship to said factor N;
• circuitry for comparing phases of said output clock, a delayed version of said output clock and said reference clock, wherein said output clock is phase-locked to said reference clock when said phase of said reference clock is between said phases of said output clock and said delayed output clock;
• and
• circuitry for outputting a signal indicating that said output clock is frequency-locked and phase-locked to said reference clock.