MOS electric fuse, its programming method, and semiconductor device using the same

A MOS electric fuse comprising:

• a semiconductor substrate;
• a well of a first conductivity type formed on an upper surface of the semiconductor substrate;
• a first impurity region and a second impurity region of a second conductivity type formed to face with each other on an upper surface of the well;
• a gate dielectric film formed on the upper surface of the well at least between the first impurity region and the second impurity region;
• and
• a gate electrode formed through the gate dielectric film on the upper surface of the well between the first impurity region and the second impurity region,
• wherein substantially binary states of conduction and nonconduction are independently set between the first impurity region and the gate electrode and between the second impurity region and the gate electrode.

A MOS electric fuse device comprising:

• a semiconductor substrate;
• a well of a first conductivity type formed on an upper surface of the semiconductor substrate;
• a first impurity region and a second impurity region, both of a second conductivity type, formed to face with each other on an upper surface of the well;
• a gate dielectric film formed on the upper surface of the well at least between the first impurity region and the second impurity region;
• and
• a gate electrode formed through the gate dielectric film on the upper surface of the well held between the first impurity region and the second impurity region,
• wherein substantially binary states of conduction and nonconduction are set only between a substantial center between the first impurity region and the second impurity region and a portion of the gate electrode opposed to the center.

A semiconductor device comprising:

• a semiconductor substrate;
• a plurality of wells of a first conductivity type formed on an upper surface of the semiconductor substrate;
• and
• a plurality of semiconductor structures formed in the plurality of wells, each of the plurality of semiconductor structures comprising
• a first impurity region and a second impurity region, both of a second conductivity type, formed to face with each other on an upper surface of each of the wells,
• a gate dielectric film formed on the upper surface of the well at least between the first impurity region and the second impurity region and having portions covering the first impurity region and the second impurity region, and
• a gate electrode formed through the gate dielectric film on the upper surface of the well held between the first impurity region and the second impurity region and having places opposed to the first impurity region and the second impurity region,
• wherein, regarding a first opposed place of the first impurity region and the gate electrode, and a second opposed place of the second impurity region and the gate electrode, there are a first state in which the first opposed place and the second opposed place are both in insulated states, a second state in which the first opposed place only is substantially short-circuited, a third state in which the second opposed place only is substantially short-circuited, and
• each of the plurality of semiconductor structures belongs to one of the first state to the third state.

A semiconductor device comprising:

• a semiconductor substrate;
• a well of a first conductivity type formed on an upper surface of the semiconductor substrate;
• a first impurity region and a second impurity region, both of a second conductivity type, formed to face with each other on an upper surface of the well;
• a gate dielectric film formed on the upper surface of the well at least between the first impurity region and the second impurity region;
• a gate electrode formed through the gate dielectric film on the upper surface of the well held between the first impurity region and the second impurity region;
• a first terminal connected to the first impurity region;
• a second terminal connected to the second impurity region;
• a third terminal connected to the gate electrode;
• a fourth terminal connected to the well;
• a first functional circuit connected to the first terminal;
• and
• a second functional circuit connected to the second terminal,
• wherein binary states of conduction and nonconduction are substantially set between the first terminal and the third terminal and between the second terminal and the third terminal.