DRAM layout with vertical FETS and method of formation
AssigneeMicron Technology, Inc.
InventorsTodd Abbott, Homer Manning
Life of this patent
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Abstract
DRAM cell arrays having a cell area of about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is orthogonal to at least one of the vertical gate electrodes of the vertical transistors.
Claims26
1-66. (canceled)
A method of forming a memory cell, comprising the steps of:
- providing a semiconductor substrate;
- providing at least one vertical transistor within the substrate, wherein the at least one vertical transistor has first, second and third doped regions;
- forming a bit line below a surface of the substrate and in connection with the first doped region of the at least one vertical transistor;
- forming a word line on sidewalls of the at least one vertical transistor so that the word line and the bit line form an angle of about ninety degree relative to each other;
- and
- providing a capacitive structure in electrical connection with the third doped region of the at least one vertical transistor.
A method of forming a memory array, comprising the steps of:
- providing a silicon-on-insulator substrate;
- forming a stack of device layers within the silicon-on-insulator substrate;
- patterning the stack of device layers to form a set of trenches in the silicon-on-insulator substrate and a plurality of columns located over the silicon-on-insulator substrate;
- forming a conductive layer within the set of trenches and over the plurality of columns;
- subjecting the conductive layer to an anneal treatment to form bit lines below a surface of the silicon-on-insulator substrate;
- forming word lines on sidewalls of the plurality of columns;
- and
- forming a capacitive structure in electrical contact with the plurality of columns.
A method of forming a memory array, comprising the steps of:
- providing a silicon substrate of a first conductivity type;
- forming a stack of device layers within the silicon substrate;
- patterning the stack of device layers to form a set of trenches in the silicon substrate and a plurality of columns located over the silicon substrate;
- forming a conductive layer within the set of trenches and over the plurality of columns;
- subjecting the conductive layer to an anneal treatment to form bit lines below a surface of the silicon substrate;
- forming word lines on sidewalls of the plurality of columns;
- and
- forming a capacitive structure in contact with the plurality of columns.
Dependencies are inferred from the claim text.