Manufacturing process of thin film transistor liquid crystal display

A thin film transistor liquid crystal display, comprising:

• a substrate comprising a thin film transistor and a capacitor disposed thereon;
• and
• a signal line comprising:
• a signal insulating layer formed on the substrate;
• a signal semiconductor layer and a signal doped silicon layer formed on the signal insulating layer;
• a signal metal layer formed on the signal doped silicon layer;
• and
• a signal transparent conducting layer formed on the signal metal layer, wherein the signal transparent conducting layer has the same pattern with the signal metal layer in the signal line.

A thin film transistor liquid crystal display, comprising:

• a substrate;
• a thin film transistor comprising:
• a gate electrode formed on the substrate;
• a transistor insulating layer and a transistor semiconductor layer formed on the gate electrode;
• a first doped silicon layer and a second doped silicon layer formed on the transistor semiconductor layer, the first doped silicon layer and the second doped silicon layer being separated by a channel area;
• a source metal layer and a source transparent conducting layer formed on the first doped silicon layer;
• and
• a drain metal layer and a drain transparent conducting layer formed on the second doped layer;
• a capacitor comprising:
• a capacitor bottom electrode formed on the substrate;
• a capacitor insulating layer and a capacitor semiconductor layer formed on the capacitor bottom electrode;
• a capacitor doped silicon layer formed on the capacitor semiconductor layer;
• and
• a capacitor metal layer and a capacitor transparent conducting layer formed on the
• capacitor doped silicon layer, and the capacitor metal layer being defined as a
• capacitor upper electrode;
• and
• a signal line comprising:
• a signal insulating layer formed on the substrate;
• a signal semiconductor layer and a signal doped silicon layer formed on the signal insulating layer;
• a signal metal layer formed on the signal doped silicon layer;
• and
• a signal transparent conducting layer formed on the signal metal layer;
• wherein a side wall of the source metal layer is substantially aligned to a sidewall of the source transparent conducting layer,
• the capacitor transparent conducting layer has a first width, the capacitor metal layer has a second width, the capacitor semiconductor layer has a third width, and the first width, the second width, and the third width are substantially the same, and
• the signal transparent conducting layer has the same pattern with the signal metal layer in the signal line.