Wafer level package, multi-package stack, and method of manufacturing the same

A method for manufacturing a semiconductor chip package, said method comprising:

• forming a through hole through a semiconductor chip, the through hole extending from an active first surface of the semiconductor chip to an opposite inactive second surface of the semiconductor chip, wherein a first conductive pad at least partially surrounds the through hole on the first surface of the semiconductor chip;
• attaching a first surface of a printed circuit board to the second surface of the chip such that a second conductive pad of the printed circuit board is aligned with the through hole of the semiconductor chip;
• and
• filling the through hole with a conductive material such that the conductive material contacts the first and second conductive pads.

A method of manufacturing a semiconductor chip package, said method comprising:

• forming a plurality of through holes through a respective plurality of semiconductor chips contained in a wafer, the through holes extending from an active first surface of the wafer to an opposite inactive second surface of the wafer, wherein a first conductive pad at least partially surrounds each through hole on the first surface of the wafer;
• forming a plurality of second conductive pads on a first surface a printed circuit board;
• attaching the first surface of a printed circuit board to the second surface of the wafer such that the plurality of second conductive pads are respectively aligned with the plurality of through holes;
• and
• filling the plurality of through holes with a conductive material such that the conductive material contacts the first and second conductive pads of each through hole.