Cascode, cascode circuit and method for vertical integration of two bipolar transistors into a cascode arrangement

A cascode comprising:

• a first transistor including a first base semiconductor region, a first collector semiconductor region, and a first emitter semiconductor region;
• and
• a second transistor including a second base semiconductor region, a second collector semiconductor region, and a second emitter semiconductor region,
• wherein the first emitter semiconductor region of the first transistor and the second collector semiconductor region of the second transistor are geometrically arranged on top with respect to a wafer surface, and
• wherein the first collector semiconductor region of the first transistor and the second emitter semiconductor region of the second transistor are geometrically arranged on a bottom with respect to the wafer surface.

A cascode circuit comprising:

• a first transistor, which is connected in a common-emitter circuit;
• and
• a second transistor, which is connected in a common-base circuit,
• wherein a collector semiconductor region of the first transistor and an emitter semiconductor region of the second transistor border on a conductive buried layer that electrically connects the collector semiconductor region of the first transistor and the emitter semiconductor region of the second transistor with one another.