P-channel electrically alterable non-volatile memory cell

A method of operating an electrically erasable and programmable nonvolatile memory device having a substrate of semiconductor material of a p-type conductivity, a well of an n-type conductivity in the substrate, an injector having a first region of the p-type conductivity and a second region of the n-type conductivity that is electrically connected to the Well, and a storage transistor comprising a source and a drain formed in the well and having the p-type conductivity, a channel of the well between the source and the drain, a charge storage region disposed over and insulated from the channel by a first insulator, and a control gate disposed over and insulated from the charge storage region by a second insulator, the method comprising the steps of:

• applying a first voltage to the first region;
• applying a second voltage to the second region;
• applying a third voltage to at least one of the source and the drain to form an inversion layer in the channel;
• and
• applying a fourth voltage to the control gate;
• wherein the second voltage is sufficiently more negative with respect to the first voltage, the third voltage is sufficiently more negative with respect to the second voltage, and the fourth voltage is sufficiently more negative with respect to the third voltage to permit holes from the injector transporting through the well through the channel through the first insulator onto the charge storage region.

A method of operating an electrically erasable and programmable nonvolatile memory device having a substrate of semiconductor material of a p-type conductivity, a well of an n-type conductivity in the substrate, an injector having a first region of the p-type conductivity and a second region of the n-type conductivity that is electrically connected to the well, and a storage transistor comprising a source and a drain formed in the well and having the p-type conductivity, a channel of the well between the source and the drain, a charge storage region disposed over and insulated from the channel by a first insulator, and a control gate disposed over and insulated from the charge storage region by a second insulator, the method comprising the steps of:

• programming the memory cell by:
• applying a first voltage to the well;
• applying a second voltage to the source;
• applying a third voltage to the drain;
• and
• applying a fourth voltage to the control gate;
• wherein the third voltage is sufficiently more negative with respect to the first voltage, and the fourth voltage is sufficiently more positive relative to the third voltage and sufficiently more negative to the second voltage to inject electrons from the channel through the first insulator onto the charge storage region;
• and
• erasing the memory cell by:
• applying a fifth voltage to the first region;
• applying a sixth voltage to the second region;
• applying a seventh voltage to at least one of the source and the drain to form an inversion layer in the channel;
• and
• applying a eighth voltage to the control gate;
• wherein the sixth voltage is sufficiently more negative with respect to the fifth voltage, the seventh voltage is sufficiently more negative with respect to the sixth voltage, and the eighth voltage is sufficiently more negative with respect to the seventh voltage to permit holes from the injector transporting through the well through the channel through the first insulator onto the charge storage region.

An electrically erasable and programmable nonvolatile memory array comprising:

• a substrate of semiconductor material of a p-type conductivity;
• a well of an n-type conductivity in the substrate;
• and
• a plurality of nonvolatile memory cells arranged in a rectangular array of rows and columns, each of the plurality of nonvolatile memory cells comprising:
• an injector having a first region of the p-type conductivity and a second region of the n-type conductivity that is electrically connected to the well;
• and
• a storage transistor comprising a source and a drain formed in the well and having the p-type conductivity, a channel of the well between the source and the drain, a charge storage region disposed over and insulated from the channel by a first insulator, and a control gate disposed over and insulated from the charge storage region by a second insulator.