Non-volatile memory device and method for manufacturing the same
AssigneeDongbuAnam Semiconductor Inc.
InventorJea-Hee Kim
Life of this patent
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Abstract
An increase of charge storing capacity, prevention of an over-erase, and a reduction of ΔVth may be achieved when a 2-bit/cell non-volatile memory device includes a gate of a predetermined width above a semiconductor substrate, an insulating layer between the gate and the semiconductor substrate and at lateral sides of the gate, having a greater width than the gate, a pair of storage layers at the lateral sides of the gate, a pair of blocking layers at the lateral sides of the gate and covering the pair of storage layers, a source and a drain formed in the semiconductor substrate at first opposed locations external to the gate, and a trap impurity implanted into the insulating layer at second locations external to the gate.
Claims20
A non-volatile memory device, comprising:
- a gate of a predetermined width above a semiconductor substrate;
- an insulating layer between the gate and the semiconductor substrate and at lateral sides of the gate, having a greater width than that of the gate;
- a pair of storage layers at the lateral sides of the gate;
- a pair of blocking layers at the lateral sides of the gate and covering the pair of storage layers;
- a source and a drain in the semiconductor substrate at first locations external to the gate;
- and
- a trap impurity implanted into the insulating layer at second locations external to the gate.
A method for manufacturing a non-volatile memory device, comprising:
- forming a bottom insulating layer on a semiconductor substrate;
- forming a gate of a predetermined width on the bottom insulating layer;
- forming a sidewall insulating layer on the gate;
- implanting a trap impurity into the bottom insulating layer at first locations external to the gate;
- forming a pair of storage layers at lateral sides of the gate;
- forming a source and a drain in the semiconductor substrate at second locations external to the pair of storage layers by ion implantation;
- and
- forming a pair of blocking layers at opposite sides of the gate and covering the pair of storage layers.
Dependencies are inferred from the claim text.