Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow

A method of forming a semiconductor structure, comprising:

• forming an insulating layer;
• forming a first layer of a first material on the insulating layer, the first layer having a first lattice spacing;
• forming a fin having a top surface and opposing sidewalls from the first layer;
• and
• forming a second layer of a second material on the fin, wherein the second layer of the second material covers the top surface and the opposing sidewalls of the fin and has a second lattice spacing, which is larger than the first lattice spacing.

A method of forming a semiconductor transistor structure, comprising:

• forming a first layer of a first material on an insulating layer on a substrate, the first layer having a first lattice spacing;
• forming a first and a second fin from the first layer, the first fin being on a first portion and the second fin being on a second portion of a semiconductor transistor structure;
• protecting a first portion of the semiconductor transistor structure with a first protective layer;
• forming a second layer of a second material having a second lattice spacing substantially larger than the first lattice spacing on the second fin;
• removing the first protective layer from the first portion of the semiconductor transistor structure and protecting the second portion of the semiconductor transistor structure with a second protective layer;
• and
• forming a third layer of a third material having a third lattice spacing substantially smaller than the first lattice spacing on the first fin.