Enhanced structure of extensible time-sharing bus
AssigneeSunplus Technology Co., Ltd.
InventorsTung-Tsai Liao, Wen-Zen Shih
Life of this patent
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Abstract
An enhanced structure of extensible time-sharing bus, which essentially uses an address and data bus in time-sharing to send addresses and data between a microprocessor and a memory through a microprocessor interface and a memory interface, and a logic combination of two control lines to determine address transfer, data read or data write on the address and data bus, thereby reducing interface pins and obtaining flexible and multiplicative memory.
Claims19
An enhanced structure of extensible time-sharing bus, which is used to data read and write between a master device and at least one slave devices, the enhanced structure comprising a master bus interface and a slave bus interface, wherein the master bus interface connects with the slave bus interface through an address and data bus and at least two control lines, the address and data bus applies time-sharing to address and data transfer between the master device and the slave device, the at least two control lines are driven to a first or second logic level by the master device such that address transfer, input and output (I/O) address, data read or data write is determined on the address and data bus by the master device and the slave device in accordance with a logic combination of the control lines.
Dependencies are inferred from the claim text.