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AssigneeThe Research Foundation of State University of New York
InventorRong Lin
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A dynamically or run-time reconfigurable matrix multiplier architecture with a reconfiguration mechanism for computing the product of matrices Xp×r and Yr×q for any integers p, q, r and any item precision b, i.e., bitwidth, ranging from 4 to 64 bits is described. The reconfigurable matrix multiplier uses borrow parallel counters with new circuits, 6—0, and 6—1 and the improved small multiplier library. The reconfigurable matrix multiplier architecture is based on a novel scheme of trading data bitwidth for processing array or matrix size. The matrix multiplier achieves an extra compact, low power, high speed design through the use of a borrow parallel counters and a library of small borrow parallel multiplier circuits. The matrix multiplying processor using area comparable with a single 64×64-b multiplier constructed of very large-scale integrated (VLSI) circuits, can be reconfigured to produce the product of two matrices X(4×4) and Y(4×4) of 8, 16, and 32-bit data items in every 1, 4, and 16 pipeline cycles, respectively, or the product of two 64-b numbers in every pipeline cycle.
A matrix multiplier circuit receiving items having bitwidth ranging from 4 to 64 bits in a plurality of pipeline cycles, the circuit comprising:
A method of using a reconfigurable matrix multiplier circuit for generating a product of at least two matrices, said circuit comprising a plurality of matrix multipliers, an arithmetic circuit including at least one borrow parallel counter and at least one 4-bit one-hot digital signal, and a reconfiguration mechanism for computing the product of said two matrices, the method comprising the steps of:
A borrow parallel counter includes 6 input bits, the counter comprising:
A method of producing a reconfigurable matrix multiplier, the method comprising the following steps:
A reconfigurable matrix multiplier comprising:
Dependencies are inferred from the claim text.