Damascene process capable of avoiding via resist poisoning

A damascene process capable of avoiding via resist poisoning, the damascene process comprising:

• providing a semiconductor substrate with a low-k dielectric layer(k≦2.9) thereon, a SiC layer over the low-k dielectric layer, a metal layer over the SiC layer, and a first bottom anti-reflection coating (BARC) layer over the metal layer;
• forming a first resist layer on the first BARC layer, wherein the first resist layer has a trench opening to expose a portion of the first BARC layer;
• etching through the first BARC layer and the metal layer and etching a portion of the SiC layer to form a trench structure in the SiC layer;
• removing the first resist layer and the first BARC layer;
• forming a blocking layer on the surface of the trench structure of the SiC layer, wherein the blocking layer is used to prevent unpolymerized precursors diffused out from the low-k dielectric layer from contacting an overlying resist;
• forming a second BARC layer on the blocking layer, the second BARC layer filling the trench structure;
• forming a second resist layer on the second BARC layer, the second resist layer having a via opening to expose a portion of the second BARC layer;
• etching through the second BARC layer ,the SiC layer, and the blocking layer, and etching a portion of the low-k dielectric layer to form a via structure in the low-k dielectric layer;
• removing the second resist layer and the second BARC layer;
• and
• performing a dual damascene process using the metal layer and the SiC layer as masks to make the low-k dielectric layer form a dual damascene structure having the trench and the via structure.