Quasi-plannar and FinFET-like transistors on bulk silicon

A quasi-planar FinFET device comprising:

• a semiconductor substrate having a top wall and at least one first recessed region of said substrate, wherein the at least one first recessed region has a side-wall and a bottom wall;
• an insulating layer partially formed in said at least one first recessed region;
• and
• at least one second recessed region juxtaposed to a top edge of said at least one first recessed region side-wall, wherein said at least one second recessed region has a depth less than said at least one first recessed region.

A method of fabricating a quasi-planar integrated circuit comprising the steps of:

• providing a silicon substrate having a top surface;
• forming at least one recessed trench region within said silicon substrate, wherein said at least one recessed trench region has a side-wall and a bottom portion, wherein said bottom portion has a bottom wall having a trench depth Td from said top surface of said silicon substrate;
• forming an insulating layer on said bottom portion of said at least one recessed trench region;
• and
• forming a doped region at said side-wall of said at least one recessed trench region.

A method of fabricating a quasi-planar transistor device comprising the steps of:

• providing a silicon substrate having a top surface;
• forming at least one first recessed trench region within said silicon substrate, said at least one first recessed region having a top wall, a side-wall and a bottom portion, wherein said bottom portion has a bottom wall having a trench depth Td from a top of said at least one first trench recess region;
• forming an insulating layer on said bottom portion of said at least one first recessed trench region;
• and
• forming a spacer recessed region within said silicon substrate, said spacer recessed region having at least two edge fins juxtaposed at two edges of said spacer recessed region.