Duty cycle correction apparatus and method for use in a semiconductor memory device

A duty cycle correction apparatus for use in a semiconductor memory device comprising:

• a delay line unit for delaying a first clock signal to produce a first delayed clock signal;
• an output tap unit for delaying the first delayed clock signal by a pulse width of a first logic state of the first delayed clock signal, under the control of a toss control signal arranged at a rising edge of a first logic state of a second clock signal which is a complementary signal of the first clock signal, to produce a delay line output clock signal arranged at a falling edge of a first logic state of the first delayed clock signal;
• and
• a phase mixer for mixing a delay line output inversion clock signal inverted from the delay line output clock signal and the first clock signal.

A duty cycle correction method for use in a semiconductor memory device comprising the steps of:

• (a) delaying a first clock signal to produce a first delayed clock signal;
• (b) delaying the first delayed clock signal by a pulse width of a first logic state of the first clock signal under the control of a toss control signal generated from a second clock signal;
• and
• (c) mixing the clock signal from the step (b) and one of the first and second clock signals.

A duty cycle correction method for use in a semiconductor memory device comprising the steps of:

• (a) delaying a first clock signal to produce a first delayed clock signal;
• (b) delaying the first delayed clock signal by a pulse width of a first logic state of the first delayed clock signal, under the control of a toss control signal arranged at a rising edge of a first logic state of a second clock signal which is a complementary signal of the first clock signal, to produce a delay line output clock signal arranged at a falling edge of a first logic state of the first delayed clock;
• and
• (c) mixing a delay line output inversion clock signal inverted from the delay line output clock signal and the first clock signal.

A semiconductor memory device having a delay lock loop (DLL) comprising:

• a delay line unit for delaying a first clock signal related to a DLL output clock signal from the DLL, to produce a first delayed clock signal;
• an output tap unit for delaying the first delayed clock signal by a pulse width of a first logic state of the first clock signal under the control of a toss control signal derived from a second clock signal;
• a phase mixer for mixing the clock signal from the output tap unit and one of the first and second clock signals;
• a phase comparator for comparing a phase of a duty cycle correction output clock signal with that of a duty cycle correction feedback clock signal, outputted from the phase mixer, to provide phase comparison signals;
• and
• a phase mixer controller for counting the number of the phase comparison signals based on the second clock signal to generate phase control signals.

A semiconductor memory device having a delay lock loop (DLL) comprising:

• a delay line means for delaying a first clock signal related to a DLL output clock signal from the DLL, to produce a first delayed clock signal;
• an output tap unit for delaying the first delayed clock signal by a pulse width of a second logic state of the first delayed clock signal, under the control of a toss control signal arranged at a rising edge of a first logic state of a second clock signal which is a complementary signal of the first clock signal, to produce a delay line output clock signal arranged at a falling edge of a first logic state of the first delayed clock signal;
• a phase mixer for mixing a delay line output inversion clock signal inverted from the delay line output clock signal and the first clock signal;
• a phase comparator for comparing a phase of a duty cycle correction output clock signal with that of a duty cycle correction feedback clock signal, outputted from the phase mixer, to provide phase comparison signals;
• and
• a phase mixer controller for counting the number of the phase comparison signals based on the second clock signal to generate phase control signals.

A semiconductor memory device comprising a delay lock loop (DLL) having an input buffering means for buffering a second clock signal being inputted from the outside,

• wherein the input buffering means includes:
• a delay line unit for delaying a first clock signal which is a complementary signal of the second clock signal, to produce a first delayed clock signal;
• an output tap unit for delaying the first delayed clock signal by a pulse width of a first logic state of the first clock signal under the control of a toss control signal generated from the second clock signal;
• a phase mixer for mixing the clock signal from the output tap unit and one of the first and second clock signals;
• a phase comparator for comparing a phase of a duty cycle correction output clock signal with that of a duty cycle correction feedback clock signal, outputted from the phase mixer, to provide phase comparison signals;
• and
• a phase mixer controller for counting the number of the phase comparison signals based on the second clock signal to generate phase control signals.

A semiconductor memory device comprising a delay lock loop (DLL) having an input buffering means for buffering a second clock signal being inputted from the outside,

• wherein the input buffering means includes:
• a delay line unit for delaying a first clock signal which is a complementary signal of the second clock signal, to produce a first delayed clock signal;
• an output tap unit for delaying the first delayed clock signal by a pulse width of a first logic state of the first delayed clock signal, under the control of a toss control signal arranged at a rising edge of a first logic state of the second clock signal, to produce a delay line output clock signal arranged at a falling edge of a pulse of a first logic state of the first delayed clock signal;
• a phase mixer for mixing a delay line output inversion clock signal inverted from the delay line output clock signal and the first clock signal;
• a phase comparator for comparing a phase of a duty cycle correction output clock signal with that of a duty cycle correction feedback clock signal, outputted from the phase mixer, to provide phase comparison signals;
• and
• a phase mixer controller for counting the number of the phase comparison signals based on the second clock signal to generate phase control signals.

A semiconductor memory device having a delay lock loop (DLL) comprising:

• an input buffer for buffering a second clock signal being inputted from the outside;
• a delay line unit for delaying a first clock signal which is a complementary signal of the second clock signal, to produce a first delayed clock signal;
• an output tap unit for delaying the first delayed clock signal by a pulse width of a first logic state of the first clock signal under the control of a toss control signal generated corresponding to the second clock signal;
• a phase mixer for mixing the clock signal from the output tap unit and one of the first and second clock signals, to thereby output a mixed clock signal onto a delay line within the DLL;
• a phase comparator for comparing a phase of a duty cycle correction output clock signal with that of a duty cycle correction feedback clock signal, outputted from the phase mixer, to provide phase comparison signals;
• and
• a phase mixer controller for counting the number of the phase comparison signals based on the second clock signal to generate phase control signals.

A semiconductor memory device having a delay lock loop (DLL) comprising:

• an input buffer for buffering a second clock signal being inputted from outside;
• a delay line unit for delaying a first clock signal which is a complementary signal of the second clock signal, to produce a first delayed clock signal;
• an output tap unit for delaying the first delayed clock signal by a pulse width of a first logic state of the first delayed clock signal, under the control of a toss control signal arranged at a rising edge of a first logic state of the second clock signal, to produce a delay line output clock signal arranged at a falling edge of a pulse of a first logic state of the first delayed clock signal;
• a phase mixer for mixing the clock signal from the output tap unit and one of the first and second clock signals, to thereby output a mixed clock signal onto a delay line within the DLL;
• a phase comparator for comparing a phase of a duty cycle correction output clock signal with that of a duty cycle correction feedback clock signal, outputted from the phase mixer, to provide phase comparison signals;
• and
• a phase mixer controller for counting the number of the phase comparison signals based on the second clock signal to generate phase control signals.