US 2005/0237808 A1 · Semiconductor memory device with MOS transistors, each including floating gate and control gate, and memory card including the same

Abstract

A semiconductor memory device includes memory cells, a memory cell array, bit lines, source lines, word lines, and select gate lines. Each of the memory cells includes a first MOS transistor having a floating gate and a control gate and a second MOS transistor having a stacked gate including a first gate electrode and a second gate electrode formed above the first gate electrode and having its drain connected to the source of the first MOS transistor. Each of the bit lines electrically connects the drains of the first MOS transistors in a same column. Each of the word lines connects the control gates of the first MOS transistors in a same row. Each of the select gate lines electrically connects the second gate electrodes of the second MOS transistors in a same row and is electrically isolated from the second gate electrodes.

Claims20

Dependent claims

A semiconductor memory device comprising:

a plurality of memory cells each of which includes a first MOS transistor having a floating gate and a control gate and a second MOS transistor having a stacked gate including a first gate electrode and a second gate electrode formed above the first gate electrode and having its drain connected to the source of the first MOS transistor;
a memory cell array in which the memory cells are arranged in a matrix;
bit lines each of which electrically connects commonly the drains of the first MOS transistors in a same column;
source lines each of which connects commonly the sources of the second MOS transistors;
word lines each of which connects commonly the control gates of the first MOS transistors in a same row;
and
select gate lines each of which electrically connects the first gate electrodes of the second MOS transistors in a same row and which is electrically isolated from the second gate electrodes.

4 more elements

A semiconductor memory device comprising:

memory cells each of which includes a first MOS transistor and a second MOS transistor,
the first MOS transistor including a source, a drain and a first stacked gate which includes a floating gate formed on a semiconductor substrate with a first gate insulating film first gate insulating film interposed therebetween and a control gate formed on the floating gate with a first inter-gate insulating film interposed therebetween, and
the second MOS transistor including the source, the drain connected to the source of the first MOS transistor and a second stacked gate which includes a first gate electrode formed on the semiconductor substrate with a second gate insulating film interposed therebetween and a second gate electrode formed on the first gate electrode with a second inter-gate insulating film interposed therebetween, the second gate electrode being in an electrically floating state;
bit lines each of which is connected to the drains of the first MOS transistors;
and
source lines each of which is connected to the sources of the second MOS transistors.

3 more elements

A semiconductor memory device comprising:

memory cells each of which includes a first NOS transistor, a second MOS transistor and third MOS transistor,
the first MOS transistor including a source, a drain and a first stacked gate which includes a floating gate formed on a semiconductor substrate with a first gate insulating film interposed therebetween and a control gate formed on the floating gate with a first inter-gate insulating film interposed therebetween,
the second MOS transistor including the source connected to the source of the first MOS transistor, the drain and a second stacked gate which includes a first gate electrode formed on the semiconductor substrate with a second gate insulating film interposed therebetween and a second gate electrode formed on the first gate electrode with a second inter-gate insulating film interposed therebetween, the second gate electrode being in an electrically floating state, and
the third MOS transistor including the source, the drain connected to the drain of the first MOS transistor, and a third stacked gate which includes a third gate electrode formed on the semiconductor substrate with a third gate insulating film interposed therebetween and a fourth gate electrode formed on the third gate electrode with a third inter-gate insulating film interposed therebetween, the fourth gate electrode being in an electrically floating state;
bit lines each of which is connected commonly to the drains of the third MOS transistors;
and
source lines each of which is connected commonly to the sources of the second MOS transistors.

4 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device with MOS transistors, each including floating gate and control gate, and memory card including the same

Life of this patent

Semiconductor memory device with MOS transistors, each including floating gate and control gate, and memory card including the same

Life of this patent

Abstract

Claims20