Operation scheme with charge balancing for charge trapping non-volatile memory
AssigneeMacronix International Co., Ltd.
InventorYen-Hao Shih
Life of this patent
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Abstract
A memory cell with a charge trapping structure has multiple bias arrangements. Multiple cycles of applying the bias arrangements lowering and raising a threshold voltage of the memory cell leave a distribution of charge in the charge trapping layer. The charge interferes with the threshold voltage achievable in the memory cell. This distribution of charge is balanced by applying a charge balancing bias arrangement at intervals during which a plurality of program and erase cycles occurs. Also, the charge balancing bias arrangement is applied prior to the beginning of program and erase cycles of the memory cell.
Claims86
A method of operating a memory cell having a threshold voltage and comprising a charge trapping structure, the method comprising:
- lowering the threshold voltage of the memory cell via a first bias arrangement and raising the threshold voltage of the memory cell via a second bias arrangement;
- and
- after an interval within which the plurality of threshold voltage raising and lowering cycles occurs or is likely to occur, applying a third bias arrangement tending to balance a distribution of charge in the charge trapping structure.
An integrated circuit device comprising:
- a semiconductor substrate;
- a plurality of memory cells on the substrate, each memory cell of the plurality of memory cells having a threshold voltage and comprising a charge trapping structure;
- and
- controller circuitry coupled to the plurality of memory cells, including logic to lower the threshold voltage via a first bias arrangement, logic to raise the threshold voltage via a second bias arrangement, and logic to change a distribution of charge in the charge trapping structure via a third bias arrangement at least after an interval within which a plurality of threshold voltage raising and lowering cycles occurs or is likely to occur.
A method of preparing a threshold voltage of a memory cell for operation, the memory cell comprising a charge trapping structure, the method comprising:
- prior to any lowering of the threshold voltage of the memory cell via a first bias arrangement of the memory cell and any raising of the threshold voltage of the memory cell via a second bias arrangement of the memory cell, adding charge to the charge trapping structure via a third bias arrangement of the memory cell.
An integrated circuit device comprising:
- a semiconductor substrate;
- a plurality of memory cells on the substrate, each memory cell of the plurality of memory cells having a threshold voltage and comprising a charge trapping structure;
- and
- controller circuitry coupled to the plurality of memory cells, including logic to lower the threshold voltage via a first bias arrangement, logic to raise the threshold voltage via a second bias arrangement, and logic to add charge to the charge trapping structure via a third bias arrangement prior at least to any threshold voltage raising and lowering cycles.
An integrated circuit device comprising:
- a substrate;
- a plurality of memory cells on the substrate, each memory cell of the plurality of memory cells having a threshold voltage and comprising a charge trapping structure, a gate, and source and drain regions in the substrate, and including a top dielectric, a charge trapping structure, and a bottom dielectric between the gate and the channel;
- and
- controller circuitry coupled to the plurality of memory cells, including logic to lower the threshold voltage via a first bias arrangement, logic to raise the threshold voltage via a second bias arrangement, and logic applying a third bias arrangement, and wherein the top dielectric, the charge trapping structure, and the bottom dielectric have a combined effective oxide thickness, and the bottom dielectric has an effective oxide thickness greater than 3 nanometers, and the third bias arrangement includes a negative voltage from the gate of the memory cell to the substrate in the region of the channel having a magnitude of about 0.7 or higher volts per nanometer of the combined effective oxide thickness.
An integrated circuit device comprising:
- a substrate;
- a plurality of memory cells on the substrate, each memory cell of the plurality of memory cells having a threshold voltage and comprising a charge trapping structure, a gate, and source and drain regions in the substrate, and including a top dielectric, a charge trapping structure, and a bottom dielectric between the gate and the channel;
- and
- controller circuitry coupled to the plurality of memory cells, including logic to lower the threshold voltage via a first bias arrangement, logic to raise the threshold voltage via a second bias arrangement, and logic applying a third bias arrangement, and wherein the top dielectric, the charge trapping structure, and the bottom dielectric have a combined effective oxide thickness, and the bottom dielectric has an effective oxide thickness about 3 nanometers or less, and the third bias arrangement includes a negative voltage from the gate of the memory cell to the substrate in the region of the channel having a magnitude of about 0.3 or higher volts per nanometer of the combined effective oxide thickness.
Dependencies are inferred from the claim text.