High voltage ESD protection circuit with low voltage transistors

An electrostatic discharge (ESD) protection circuit having only low voltage transistors, the circuit comprising:

• a stacked NMOS transistor pair coupled between a pad and a negative voltage supply with a first transistor's drain connected to the pad and a second transistor's source connected to the negative power supply;
• a first voltage divider providing a reduced voltage from a high voltage positive power supply to a gate of the first transistor;
• a first diode string coupled between the gates of the first and second transistors;
• an inverter with a source of a PMOS transistor thereof coupled to the pad and with its NMOS transistor coupled to the negative power supply, along with an output node of the inverter being coupled to a gate of the second transistor;
• and
• a RC circuit coupled to an input node of the inverter,
• wherein an ESD current travels through the stacked NMOS transistor pair for dissipation.

A circuit with high voltage power supply integrated with an electrostatic discharge (ESD) protection mechanism using low voltage transistors, the circuit comprising:

• an ESD protection circuit using only low voltage transistors, the ESD protection circuit further comprising:
• a stacked NMOS transistor pair coupled between a pad and a negative voltage supply with a first transistor's drain connected to the pad and a second transistor's source connected to the negative power supply;
• a first voltage divider providing a reduced voltage from a high voltage positive power supply to a gate of the first transistor;
• a first diode string coupled between the gates of the first and second transistors;
• a second diode string with its anode end coupled to the pad;
• an inverter with a source of a PMOS transistor thereof coupled to a cathode end of the second diode string and with its NMOS transistor coupled to the negative power supply, along with an output node of the inverter being coupled to a gate of the second transistor;
• and
• a RC circuit coupled to an input node of the inverter;
• and
• an application circuit using the high voltage power supply as its operation voltage;
• wherein an ESD current initiated from the application circuit travels through the stacked NMOS transistor pair of the ESD protection circuit for dissipation.