Minimizing transistor variations due to shallow trench isolation stress

A Metal Oxide Semiconductor (MOS) transistor, comprising:

• an active area in a substrate;
• an isolation structure in said substrate and surrounding said active area;
• and
• at least one stress adjustor adjacent said active area, wherein said stress adjustor is positioned to modify a mobility of a majority carrier within a channel region of said MOS transistor.

A process for constructing an integrated circuit (IC), including:

• generating a mask layout for an IC, comprising:
• calculating an active overlap distance between a planned perimeter of a gate of said IC and a planned perimeter of an active area of said IC;
• determining a compressive stress along a direction of an intended current flow through a planned channel of said IC based on said active overlap distance;
• and
• introducing a stress adjustor area adjacent said active area to modify a mobility of a majority carrier through said planned channel, if said compressive stress is greater than a critical stress parameter;
• and
• using said mask layout to produce said IC.