Implementation of wide multiplexers in reconfigurable logic

Abstract

A reconfigurable processing device comprising one or more reconfigurable processing units is disclosed. At least a processing unit includes a computational unit having a preprocessing module for receiving n input signals, and s1 selection signals, and providing k output signals wherein k<n+s1. The computational unit further comprises a m-output look-up table being addressed by the k output signals of the preprocessing module and an output multiplexer for selecting one of the m output signals of the look-up table under control of s2 further selection signals. This allows for the implementation of relatively large multiplexers also in architectures using multi-bit output LUTs. In addition a reconfigurable processing unit is described having an input multiplexer for selecting input signal from a communication network, which input multiplexer is configurable statically or dynamically.

Dependencies are inferred from the claim text.