Semiconductor device having a low-resistance bus interconnect, method of manufacturing same, and display apparatus employing same

A semiconductor device comprising:

• a substrate;
• a plurality of circuit units disposed on said substrate and including thin-film transistors, said circuit units having respective output terminals;
• at least one bus interconnect for supplying a voltage to said circuit units;
• and
• a power supply feed point for supplying a voltage from an external source to said bus interconnect;
• wherein said circuit units include circuit units disposed on a left-hand side of said power supply feed point and remaining circuit units disposed on a right-hand side of said power supply feed point, and a pitch L (m) of said circuit units, a number N of said circuit units, and a resistance R (Ω/m) per unit length of said at least one bus interconnect are related to each other as follows:
• R×N2×L≦16×103

A method of manufacturing a semiconductor device, comprising the steps of:

• forming N circuit units including thin-film transistors at a pitch L (m), on a substrate;
• and
• forming output terminals of said circuit units and at least one bus interconnect for supplying a voltage to said circuit units, wherein the pitch L (m) of said circuit units, the number N of said circuit units, and a resistance R (Ω/m) per unit length of said at least one bus interconnect are related to each other as follows:
• R×N2×L≦4×103
• wherein said step of forming output terminals of said circuit units and at least one bus interconnect includes the step of simultaneously forming at least a portion of said bus interconnect and at least a portion of said output terminals.

A method of manufacturing a semiconductor device, comprising the steps of:

• forming N circuit units including thin-film transistors at a pitch L (m), on a substrate;
• and
• forming output terminals of said circuit units and at least one bus interconnect for supplying a voltage to said circuit units, wherein the pitch L (m) of said circuit units, the number N of said circuit units, and a resistance R (Ω/m) per unit length of said at least one bus interconnect are related to each other as follows:
• R×N2×L≦16×103
• wherein said step of forming output terminals of said circuit units and at least one bus interconnect includes the step of simultaneously forming at least a portion of said bus interconnect and at least a portion of said output terminals.