US 2005/0232009 A1 · CMIS semiconductor nonvolatile storage circuit

Abstract

A nonvolatile semiconductor memory circuit includes a selection line, a first bit line, a second bit line, a first MIS transistor having a first gate coupled to the selection line, a first drain coupled to the first bit line via a first node, and a first source coupled to a predetermined potential, a second MIS transistor having a second gate coupled to the selection line, a second drain coupled to the second bit line via a second node, and a second source coupled to the predetermined potential, and a latch circuit coupled to the first node and the second node to store data responsive to a signal difference between the first node and the second node, wherein the selection line is operative to supply a write potential that creates a lingering change in a threshold voltage of one of the first MIS transistor and the second MIS transistor.

Claims33

Dependent claims

A nonvolatile semiconductor memory circuit, comprising:

a selection line;
a first bit line;
a second bit line;
a first MIS transistor having a first gate coupled to said selection line, a first drain coupled to the first bit line via a first node, and
a first source coupled to a predetermined potential;
a second MIS transistor having a second gate coupled to said selection line, a second drain coupled to the second bit line via a second node, and a second source coupled to said predetermined potential;
and
a latch circuit coupled to the first node and the second node to store data responsive to a signal difference between the first node and the second node,
wherein the selection line is operative to supply a write potential that creates a lingering change in a threshold voltage of one of the first MIS transistor and the second MIS transistor.

6 more elements

A nonvolatile semiconductor memory device, comprising:

a plurality of bit-line pairs;
a plurality of memory units arranged in a matrix, one of said memory units coupled to a corresponding one of said bit-line pairs, said corresponding one of said bit-line pairs including a first bit line and a second bit line, said one of said memory units including:
a selection line;
a first MIS transistor having a first gate coupled to said selection line, a first drain coupled to the first bit line via a first node, and a first source coupled to a predetermined potential;
a second MIS transistor having a second gate coupled to said selection line, a second drain coupled to the second bit line via a second node, and a second source coupled to said predetermined potential;
and
a latch circuit coupled to the first node and the second node to store data responsive to a signal difference between the first node and the second node,
wherein the selection line is operative to supply a write potential that creates a lingering change in a threshold voltage of one of the first MIS transistor and the second MIS transistor.

5 more elements

A nonvolatile semiconductor memory device, comprising:

a plurality of bit-line pairs;
a plurality of memory units arranged in a matrix, one of said memory units coupled to a corresponding one of said bit-line pairs, said corresponding one of said bit-line pairs including a first bit line and a second bit line, said one of said memory units including:
a selection line;
a first MIS transistor having a first gate coupled to said selection line, a first drain coupled to the first bit line via a first node, and a first source coupled to a predetermined potential;
a second MIS transistor having a second gate coupled to said selection line, a second drain coupled to the second bit line via a second node, and a second source coupled to said predetermined potential;
and
a latch circuit coupled to the first node and the second node to store data responsive to a signal difference between the first node and the second node,
wherein the selection line is operative to supply a write potential that creates a lingering change in a resistance of one of the first MIS transistor and the second MIS transistor.

5 more elements

A nonvolatile semiconductor memory circuit, comprising two MISFET-type transistors having substantially same characteristics, characterized in that a conductive state of the first transistor is controlled by controlling a voltage of a gate electrode of the first transistor to be a voltage other than a power supply potential and a ground potential for a predetermined period, thereby inducing a secular deterioration in an on-resistance thereof, which causes a performance difference between the first and second transistors, the performance difference being read as a current difference between the two transistors simultaneously made conductive, thereby storing and reading “0”, and, conversely, a performance of the second transistor is degraded greater than the first transistor, thereby storing “1”.

Dependencies are inferred from the claim text.

CMIS semiconductor nonvolatile storage circuit

Life of this patent

CMIS semiconductor nonvolatile storage circuit

Life of this patent

Abstract

Claims33