Multilayer printed board, electronic apparatus, and packaging method
OwnerHideki Koyamainventor
Life of this patent
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Abstract
A multilayer printed board comprising a plurality of capacitive coupling layers (6) each consisting of a dielectric layer (4) and a power supply layer (3) and a ground layer (5) facing each other while sandwiching the dielectric layer (4), first vias (7) connecting between the power supply layers (3) included in the plurality of capacitive coupling layers (6), and second vias (8) connecting between the ground layers (5) included in the plurality of capacitive coupling layers (6).
Claims17
A multilayer printed board, comprising:
- a plurality of capacitive coupling layers, each of which includes a power supply layer and a ground layer which are opposed to each other and a dielectric layer which is sandwiched therebetween;
- a first via that connects between the power supply layers included in the plurality of capacitive coupling layers;
- and
- a second via that connects between the ground layers included in the plurality of capacitive coupling layers.
A multilayer printed board, wherein the number of the second via is equal to or more than twice the number of the first via.
A multilayer printed board, comprising:
- a capacitive coupling layer that includes a power supply layer and a ground layer which are opposed to each other and a dielectric layer which is sandwiched therebetween;
- an element layer on which an element to which power is supplied from the power supply layer is mounted;
- and
- a via that is formed close to a central axis passing through substantially a central portion of a flat region of the capacitive coupling layer and connects a power supply terminal of the element with the power supply layer.
An electronic apparatus in which a multilayer printed board is provided, the multilayer printed board comprising:
- a capacitive coupling layer that includes a power supply layer and a ground layer which are opposed to each other and a dielectric layer which is sandwiched therebetween;
- an element layer on which an element to which power is supplied from the power supply layer is mounted;
- and
- a via that is formed close to a central axis passing through substantially a central portion of a flat region of the capacitive coupling layer and connects a power supply terminal of the element with the power supply layer.
A method of packaging an electronic apparatus, comprising:
- a step producing a plurality of capacitive coupling layers, each of which includes a power supply layer and a ground layer which are opposed to each other and a dielectric layer which is sandwiched therebetween;
- a first via connecting step connecting between the power supply layers included in the plurality of capacitive coupling layers through a first via;
- and
- a second via connecting step connecting between the ground layers included in the plurality of capacitive coupling layers through a second via, the number of which is equal to or more than twice the number of the first via.
A method of packaging an electronic apparatus, comprising:
- a capacitive coupling step forming a capacitive coupling layer that includes a power supply layer and a ground layer which are opposed to each other and a dielectric layer which is sandwiched therebetween;
- a step forming an element layer on which an element to which power is supplied from the power supply layer is mounted;
- and
- a step forming a via that connects a power supply terminal of the element with the power supply layer at a vicinity of a central axis passing through substantially a central portion of a flat region of the capacitive coupling layer.
Dependencies are inferred from the claim text.