Method of implementing polishing uniformity and modifying layout data
AssigneeFreescale Semiconductor, Inc.
InventorsEdward Travis, Nathan Aldrich, Ruiqi Tian
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AssigneeFreescale Semiconductor, Inc.
InventorsEdward Travis, Nathan Aldrich, Ruiqi Tian
Estimating the term…
A method for identifying areas of low overburden which degrade (increase) metal polish nonuniformity is discussed. Also described is a method for modifying these areas to increase their overburden, thus slowing down the metal polish rate and improving overall polish uniformity. The resulting structure forms slots in groups of functional lines, such as bus lines, when the functional lines have a density prior to forming the slots that exceeds a predetermined amount. In one embodiment, an area of the wafer has a maximum width of 1.5 microns in an area that has a feature density greater than approximately 50 percent. The methods and resulting structures create a higher feature density, thereby increasing polishing uniformity.
A method of implementing polishing uniformity, said method comprising:
A method of implementing polishing uniformity control for a material on a substrate to be polished, said method comprising:
A method for modifying layout data of a material on a substrate for improving a polishing uniformity of the material on the substrate during a polishing of the same, said method comprising:
A method of modifying a layout design of a material on a substrate for improving a polishing uniformity of the same, said method comprising:
A method for forming a semiconductor device comprising:
Dependencies are inferred from the claim text.