No-instruction-set-computer processor

Abstract

A no-instruction-set-computer (NISC) processor in combination with a program counter, program memory and data memory comprises a controller coupled to the program memory; and a datapath coupled to the controller and to the data memory, characterized in that computer code compiles directly into the controller and the datapath. The datapath comprises a plurality of storage elements, a plurality of functional units and a plurality of busses. The plurality of storage elements and functional units are selectively coupled together by the plurality of busses. The datapath collectively generate datapath output, and status signals and have a data memory input. The controller has no instruction set and computer code runs directly on the controller. The processor is combined with a compiler which is arranged and configured to operate a parse tree. Under control of the compiler the controller covers the parse tree with control words stored in the program memory.

Dependencies are inferred from the claim text.