Vectorization in a SIMdD DSP architecture

A method for determining vectorization configurations in a computer processor architecture for computations that feature arbitrary parametric access, the method comprising:

• identifying a loop in a computer program that accesses data indirectly;
• determining that indices of said loop fit within the range of a vector element file of said architecture, and, if so:
• loading all loop data into said vector element file;
• loading said indices into at least one vector pointer register of said architecture in support of reorder-on-read use of said vector element file;
• and
• vectorizing said loop data.

A system for determining vectorization configurations in a computer processor architecture, the system comprising:

• means for identifying a vectorizable loop in a computer program;
• means for identifying a memory access pattern of data required for implementing said loop in said architecture;
• means for computing a set of candidate configurations of resources required for vectorizing said data in said architecture, wherein said means for computing step is operative to configure a vector pointer register of said architecture in support of either of reorder-on-read use and reorder-on-write use of a vector element file of said architecture;
• means for selecting one of said candidates in accordance with predefined selection criteria;
• and
• means for implementing said selected vectorization configuration in said architecture.

A system for determining vectorization configurations in a computer processor architecture for computations that feature arbitrary parametric access, the system comprising:

• means for identifying a loop in a computer program that accesses data indirectly;
• means for determining that indices of said loop fit within the range of a vector element file of said architecture, and, if so:
• means for loading all loop data into said vector element file;
• means for loading said indices into at least one vector pointer register of said architecture in support of reorder-on-read use of said vector element file;
• and
• means for vectorizing said loop data.

A computer program embodied on a computer-readable medium, the computer program comprising:

• a first code segment operative to identify a vectorizable loop in a computer program;
• a second code segment operative to identify a memory access pattern of data required for implement said loop in said architecture;
• a third code segment operative to compute a set of candidate configurations of resources required for vectorizing said data in said architecture and configure a vector pointer register of said architecture in support of either of reorder-on-read use and reorder-on-write use of a vector element file of said architecture;
• a fourth code segment operative to select one of said candidates in accordance with predefined selection criteria;
• and
• a fifth code segment operative to implement said selected vectorization configuration in said architecture.

A computer program embodied on a computer-readable medium, the computer program comprising:

• a first code segment operative to identify a loop in a computer program that accesses data indirectly;
• a second code segment operative to determin that indices of said loop fit within the range of a vector element file of said architecture, and, if so, load all loop data into said vector element file;
• a third code segment operative to load said indices into at least one vector pointer register of said architecture in support of reorder-on-read use of said vector element file;
• and
• a fourth code segment operative to vectorize said loop data.