Processor
AssigneeSeiko Epson Corporation
InventorMasanobu Seki
Life of this patent
Estimating the term…
Abstract
In a processor, an ALU or a decode portion comprises a sign reversal portion 101 for reversing the sign of a first input value, a sign determination portion 102 for determining the sign of a second input value, and an output selection portion 103 for selectively outputting the first input value, if the determination result of the sign determination portion 102 is positive, selectively outputting the value inputted from the sign reversal section, if it is negative, or outputting zero if it is zero.
Claims4
A processor having a decode portion for decoding the fetched data, and a processing portion for performing an operation based on the decoded result, wherein at least one of said decode portion and said processing portion comprises:
- a sign reversal section for reversing the sign of a first input value;
- a sign determination section for determining the sign of a second input value;
- and
- an output selection section for selectively outputting said first input value, if the determination result of said sign determination section is positive, selectively outputting the value inputted from said sign reversal section, if it is negative, or outputting zero if it is zero.
Dependencies are inferred from the claim text.