US 2005/0088906 A1 · Semiconductor memory device having different synchronizing timings depending on the value of CAS latency

Abstract

A semiconductor memory device including a clock buffer, a column selection line decoder, a control signal generation circuit, and a column selection line driver is provided. The clock buffer receives an external clock signal and information about a column address strobe (CAS) latency and generates either a first clock signal which synchronizes with rising edges of the external clock signal or a second clock signal which synchronizes with falling edges of the external clock signal depending on the type of CAS latency information. The column selection line decoder receives and decodes a column selection address and outputs a decoding address used to select either a column selection line signal synchronized with the first or second clock signal. The control signal generation circuit outputs control signals that synchronize with one of the first and second clock signals. The column selection line driver drives the column selection line signal in synchronization with one of the first and second clock signal in response to the decoding address and the control signals.

Claims16

Dependent claims

A semiconductor memory device comprising:

a clock buffer receiving an external clock signal and information about a column address strobe (CAS) latency and generating either a first clock signal which synchronizes with rising edges of the external clock signal or a second clock signal which synchronizes with falling edges of the external clock signal depending on the type of CAS latency information;
a column selection line decoder receiving and decoding a column selection address and outputting a decoding address used to select either a column selection line signal synchronized with the first or second clock signal;
a control signal generation circuit outputting control signals that synchronize with one of the first and second clock signals;
and
a column selection line driver driving the column selection line signal in synchronization with one of the first and second clock signal in response to the decoding address and the control signals.

2 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device having different synchronizing timings depending on the value of CAS latency

Life of this patent

Semiconductor memory device having different synchronizing timings depending on the value of CAS latency

Life of this patent

Abstract

Claims16