SOI device with reduced junction capacitance
AssigneeInternational Business Machines Corporation
InventorToshiharu Furukawa
Life of this patent
Estimating the term…
Abstract
An SOI FET comprising a silicon substrate having silicon layer on top of a buried oxide layer having doped regions and an undoped region is disclosed. The doped region has a dielectric constant different from the dielectric constant of the doped regions. A body also in the silicon layer separates the source/drains in the silicon layer. The source/drains are aligned over the doped regions and the body is aligned over the undoped region. A gate dielectric is on top of the body and a gate conductor is on top of the gate dielectric.
Claims20
A semiconductor structure comprising:
- a silicon substrate having a first dielectric layer therein, said first dielectric layer having a first region and a second region, said second layer having implanted fluorine therein, said first region having a first dielectric constant and said second region having a second dielectric constant less than said first dielectric constant.
(canceled)
5-11. (canceled)
A method of fabricating a semiconductor structure, comprising the steps of:
- providing a silicon substrate having a first dielectric layer therein;
- forming a first region in said dielectric layer, said first region having a first dielectric constant;
- and
- after the step of providing the silicon substrate having the first dielectric layer therein, forming a second region in said first dielectric layer by implanting fluorine in said dielectric layer to form said second region as a fluorinated region, said second region having a second dielectric constant less than said first dielectric constant.
(canceled)
17-29. (canceled)
Dependencies are inferred from the claim text.