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US 2005/0087787 A1Published application
Semiconductor device and manufacturing method thereof
AssigneeFujitsu Limited
InventorTakashi Ando
Life of this patent
Estimating the term…
Abstract
There is formed a gate electrode (word line) via a gate insulating film on a semiconductor substrate, the gate electrode extending in the direction inclining at an angle of approximately 45 degrees to the extending direction of an element region. The element region is divided into three portions by the two gate electrodes. In each element region portion, two MOS transistors are provided. A bit line is connected to a W plug provided in the central region portion and lower electrodes of two ferroelectric capacitors are connected to other W plugs provided in both end region portions. The extending direction of the bit line inclines approximately 45 degrees to the extending direction of the element region.
Claims30
A semiconductor device comprising:
- a semiconductor substrate;
- a plurality of transistors formed on a surface of said semiconductor substrate;
- an interlayer insulating film for covering said transistors;
- and
- a plurality of ferroelectric capacitors formed over said interlayer insulating film, an electrode of each of said plurality of ferroelectric capacitors being connected to one of a source or a drain of said transistor via a first contact plug,
- wherein said plurality of ferroelectric capacitors are arranged in an array,
- wherein each of said plurality of ferroelectric capacitor has substantially a rectangular planar shape, and
- wherein the ratio between the length of a long side of the rectangular shape and the distance between the long sides of two ferroelectric capacitors adjacent to each other substantially coincides with the ratio between the length of a short side of the rectangular shape and the distance between the short sides of two ferroelectric capacitors adjacent to each other.
5 more elements
A semiconductor device comprising:
- a semiconductor substrate;
- a plurality of transistors formed on a surface of said semiconductor substrate;
- an interlayer insulating film for covering said transistors;
- a plurality of ferroelectric capacitors formed over said interlayer insulating film, an electrode of each of said plurality of ferroelectric capacitors being connected to one of a source or a drain of said transistor via a first contact plug;
- and
- a plurality of bit lines formed over said interlayer insulating film, each of said plurality of bit lines being connected to the other one of the source or the drain of said transistor via a second contact plug;
- wherein said plurality of ferroelectric capacitors are arranged in an array, and
- wherein the first contact plug is located at substantial central point of a minimal rectangular shape made by four ferroelectric capacitors out of said plurality of ferroelectric capacitors.
5 more elements
A semiconductor device comprising:
- a semiconductor substrate;
- a plurality of transistors formed on a surface of said semiconductor substrate;
- an interlayer insulating film for covering said transistors;
- a plurality of ferroelectric capacitors formed over said interlayer insulating film, an electrode of each of said plurality of ferroelectric capacitors being connected to one of a source or a drain of said transistor via a first contact plug;
- and
- a plurality of bit lines formed over said interlayer insulating film, each of said plurality of bit lines being connected to the other one of the source or the drain of said transistor via a second contact plug,
- wherein said plurality of ferroelectric capacitors are arranged in an array,
- wherein each of said ferroelectric capacitors has substantially a rectangular planar shape, and
- wherein the second contact plug is located between respective long sides of two adjacent ferroelectric capacitors out of said plurality of ferroelectric capacitors.
6 more elements
A semiconductor device comprising:
- a semiconductor substrate;
- a plurality of transistors formed on a surface of said semiconductor substrate;
- an interlayer insulating film for covering said transistors;
- and
- a plurality of ferroelectric capacitors formed over said interlayer insulating film, an electrode of each of said plurality of ferroelectric capacitors being connected to one of a source or a drain of said transistor via a first contact plug,
- wherein each of said ferroelectric capacitors has substantially a circular planar shape.
3 more elements
A manufacturing method of a semiconductor device, comprising the steps of:
- forming a plurality of transistors on a surface of a semiconductor substrate;
- forming an interlayer insulating film for covering the transistors;
- and
- forming a plurality of ferroelectric capacitors over the interlayer insulating film, an electrode of each of the plurality of ferroelectric capacitors being connected to one of a source or a drain of the transistor via a first contact plug,
- wherein the plurality of ferroelectric capacitors are arranged in an array,
- wherein each of the plurality of ferroelectric capacitors has substantially a rectangular planar shape, and
- wherein the ratio between the length of a long side of the rectangular shape and the distance between the long sides of two ferroelectric capacitors adjacent to each other substantially coincides with the ratio between the length of a short side of the rectangular shape and the distance between the short sides of two ferroelectric capacitors adjacent to each other.
4 more elements
A manufacturing method of a semiconductor device, comprising the steps of:
- forming a plurality of transistors on a surface of a semiconductor substrate;
- forming an interlayer insulating film for covering the transistors;
- forming a plurality of ferroelectric capacitors over the interlayer insulating film, an electrode of each of the plurality of ferroelectric capacitors being connected to one of a source or a drain of the transistor via a first contact plug;
- and
- forming a plurality of bit lines over said interlayer insulating film, each of said plurality of bit lines being connected to the other one of the source or the drain of said transistor via a second contact plug,
- wherein the plurality of ferroelectric capacitors are arranged in an array, and
- wherein the first contact plug is located at substantial central point of a minimal rectangular shape made by four ferroelectric capacitors out of the plurality of ferroelectric capacitors.
4 more elements
A manufacturing method of a semiconductor device, comprising the steps of:
- forming a plurality of transistors on a surface of a semiconductor substrate;
- forming an interlayer insulating film for covering the transistors;
- forming a plurality of ferroelectric capacitors over the interlayer insulating film, an electrode of each of the plurality of ferroelectric capacitors being connected to one of a source or a drain of the transistor via a first contact plug;
- and
- forming a plurality of bit lines over said interlayer insulating film, each of said plurality of bit lines being connected to the other one of the source or the drain of said transistor via a second contact plug,
- wherein the plurality of ferroelectric capacitors are arranged in an array,
- wherein each of the plurality of ferroelectric capacitors has substantially a rectangular planar shape, and
- wherein the second contact plug is located between respective long sides of two adjacent ferroelectric capacitors out of the plurality of ferroelectric capacitors.
5 more elements
A manufacturing method of a semiconductor device, comprising the steps of:
- forming a plurality of transistors on a surface of a semiconductor substrate;
- forming an interlayer insulating film for covering the transistors;
- and
- forming a plurality of ferroelectric capacitors over the interlayer insulating film, an electrode of each of the plurality of ferroelectric capacitors being connected to one of a source or a drain of the transistor via a first contact plug,
- wherein each of the plurality of ferroelectric capacitors has substantially a circular planar shape.
2 more elements
Dependencies are inferred from the claim text.