Recess gate transistor structure for use in semiconductor device and method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorJi-Young Kim
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AssigneeSamsung Electronics Co., Ltd.
InventorJi-Young Kim
Estimating the term…
An inner spacer is formed in a sidewall of a gate in contact with a first active region that is electrically connected to an upper capacitor, thereby reducing a gate induced drain leakage (GIDL). A structure of a recess gate transistor includes a gate insulation layer, a gate electrode, a first gate spacer, a second gate spacer and source/drain regions. The gate insulation layer is formed within a recess. The gate electrode is surrounded by the gate insulation layer and is extended from within the recess. The first gate spacer is spaced with a predetermined distance horizontally with a portion of the gate insulation layer, being formed in a sidewall of the gate electrode. The second gate spacer is formed in another part of the sidewall of the gate electrode. The source/drain regions are formed mutually oppositely on first and second active regions with the gate electrode therebetween.
A recess gate transistor formed on a substrate having a device isolation film that defines an active region and a non-active region, the active region being sub-defined by a recess as a first active region and a second active region, the transistor comprising:
A transistor of recess gate transistor formed on a substrate having a device isolation film that defines an active region and a non-active region, the active region being sub-defined by a recess as a first active region and a second active region, the transistor comprising:
A method of forming a recess gate transistor on a substrate having a device isolation film that defines an active region and a non-active region, the method comprising:
Dependencies are inferred from the claim text.