Method and apparatus for determining gate-level delays in an integrated circuit

A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for determining a voltage at the output of a gate in an integrated circuit, the method comprising:

• receiving a design for the integrated circuit;
• locating a gate within the integrated circuit;
• and
• looking up a set of output current waveforms for the gate assuming a given input slew, wherein each output current waveform specifies output current as a function of time for a different effective capacitance at the output of the gate;
• applying each output current waveform to its corresponding effective capacitance to calculate a first set of output voltages;
• applying each output current waveform to an RC(L) network to calculate a second set of output voltages, wherein the RC(L) network models the RC(L) characteristics of a net coupled to the output of the gate;
• and
• for each time step in a series of time steps,
• selecting an output current waveform for which a voltage obtained by evaluating a corresponding waveform in the first set of output voltages at the current time step matches a voltage obtained by evaluating a corresponding waveform in the second set of output voltages at the current time step, and
• applying the selected output current waveform to the RC(L) network to update a present voltage at the output of the gate.

An apparatus for determining a voltage at the output of a gate in an integrated circuit, comprising:

• a receiving mechanism configured to receive a design for the integrated circuit;
• a locating mechanism configured to locate a gate within the integrated circuit;
• and
• a look-up mechanism configured to look up a set of output current waveforms for the gate assuming a given input slew, wherein each output current waveform specifies output current as a function of time for a different effective capacitance at the output of the gate;
• an applying mechanism configured to apply each output current waveform to its corresponding effective capacitance to calculate a first set of output voltage waveforms;
• wherein the applying mechanism is further configured to apply each output current waveform to an RC(L) network to calculate a second set of voltage output waveforms, wherein the RC(L) network models the RC(L) characteristics of a net coupled to the output of the gate;
• a selecting mechanism configured to select an output current waveform for which a voltage obtained by evaluating a corresponding waveform in the first set of output voltage waveforms at the current time step matches a voltage obtained by evaluating a corresponding waveform in the second set of output voltage waveforms at the current time step for each time step in a series of time steps;
• and
• wherein the applying mechanism is further configured to apply the selected output current waveform to the RC(L) network to update a present voltage at the output of the gate.