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US 2005/0037584 A1Published application
Methods of forming a transistor with an integrated metal silicide gate electrode
AssigneeMicron Technology, Inc.
InventorTodd Abbott
Life of this patent
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Abstract
Methods of forming a transistor having integrated metal silicide transistor gate electrode on a semiconductor assembly are described. The transistor gate is partially fabricated by reacting the metal with epitaxial silicon while residing in a trench to form metal silicide. A transistor gate isolation capping layer is formed in the trench and on the metal silicide. Optional trench spacers can be added to reduce the critical dimension restraints of a given fabrication process and thus form a transistor having smaller feature sizes than the critical dimension.
Claims30
A method of forming a transistor on a semiconductor assembly comprising:
- forming a trench in an isolation material overlying a silicon layer, a transistor gate oxide layer and a silicon substrate material;
- forming silicon and metal inside the trench;
- reacting the metal with the silicon to form metal silicide inside the confines of the trench while preventing the formation of metal silicide in the silicon layer outside the confines of the trench;
- forming a transistor isolation cap over the metal silicide;
- removing the isolation material and underlying regions of the silicon layer and the transistor gate oxide to form a transistor gate stack comprising the transistor isolation cap, the metal silicide, a portion of the silicon layer and the transistor gate oxide;
- and
- forming source/drain regions of the transistor in the silicon substrate material and on opposing sides of the transistor gate stack.
4 more elements
A method of forming a transistor on a semiconductor assembly comprising:
- providing a substrate having isolation regions formed into a conductive silicon substrate with an oxide layer formed thereon;
- forming a polysilicon layer on the oxide layer;
- forming a trench isolation material over the polysilicon layer;
- forming a patterned photoresist having an opening therein over the trench isolation material;
- etching a trench into the trench isolation material through the opening and exposing a portion of the underlying polysilicon layer;
- growing epitaxial silicon into the bottom of the trench on the exposed portion of the underlying polysilicon layer;
- depositing a metal layer along the sidewalls of the trench and on the epitaxial silicon;
- performing a first anneal on the semiconductor assembly to cause the metal layer to react with the epitaxial silicon to form metal silicide;
- removing any un-reacted metal layer;
- performing a second anneal step to continue the formation of metal silicide;
- depositing an isolation capping material into the trench and over the metal silicide;
- removing the lateral component of the isolation capping material;
- etching selectively to the isolation capping material to form a transistor gate stack comprising a transistor isolation cap, the metal silicide, a portion of the silicon layer and the transistor gate oxide;
- implanting conductive dopants into the conductive silicon substrate to form self-aligned lightly doped source/drain regions of the transistor;
- forming transistor gate sidewall isolation spacers;
- and
- implanting conductive dopants into the conductive silicon substrate to form source/drain regions of the transistor.
14 more elements
A method of forming a semiconductor memory device having a transistor comprising:
- providing a substrate having isolation regions formed into a conductive silicon substrate with an oxide layer formed thereon;
- forming a polysilicon layer on the oxide layer;
- forming a trench isolation material over the polysilicon layer;
- forming a patterned photoresist having an opening therein over the trench isolation material;
- etching a trench into the trench isolation material through the opening and exposing a portion of the underlying polysilicon layer;
- growing epitaxial silicon into the bottom of the trench on the exposed portion of the underlying polysilicon layer;
- depositing a metal layer along the sidewalls of the trench and on the epitaxial silicon;
- performing a first anneal on the semiconductor assembly to cause the metal layer to react with the epitaxial silicon to form metal silicide;
- removing any un-reacted metal layer;
- performing a second anneal step to continue the formation of metal silicide;
- depositing an isolation capping material into the trench and over the metal silicide;
- removing the lateral component of the isolation capping material;
- etching selectively to the isolation capping material to form a transistor gate stack comprising a transistor isolation cap, the metal silicide, a portion of the silicon layer and the transistor gate oxide;
- implanting conductive dopants into the conductive silicon substrate to form self-aligned lightly doped source/drain regions of the transistor;
- forming transistor gate sidewall isolation spacers;
- and
- implanting conductive dopants into the conductive silicon substrate to form source/drain regions of the transistor.
14 more elements
A method of forming a semiconductor assembly having a transistor comprising:
- providing a substrate having isolation regions formed into a conductive silicon substrate with an oxide layer formed thereon;
- forming a polysilicon layer on the oxide layer;
- forming a trench isolation material over the polysilicon layer;
- forming a patterned photoresist having an opening therein over the trench isolation material;
- etching a trench into the trench isolation material through the opening and exposing a portion of the underlying polysilicon layer;
- growing epitaxial silicon into the bottom of the trench on the exposed portion of the underlying polysilicon layer;
- depositing a metal layer along the sidewalls of the trench and on the epitaxial silicon;
- performing a first anneal on the semiconductor assembly to cause the metal layer to react with the epitaxial silicon to form metal silicide;
- removing any un-reacted metal layer;
- performing a second anneal step to continue the formation of metal silicide;
- depositing an isolation capping material into the trench and over the metal silicide;
- removing the lateral component of the isolation capping material;
- etching selectively to the isolation capping material to form a transistor gate stack comprising a transistor isolation cap, the metal silicide, a portion of the silicon layer and the transistor gate oxide;
- implanting conductive dopants into the conductive silicon substrate to form self-aligned lightly doped source/drain regions of the transistor;
- forming transistor gate sidewall isolation spacers;
- and
- implanting conductive dopants into the conductive silicon substrate to form source/drain regions of the transistor.
14 more elements
A method of forming semiconductor system having a transistor comprising:
- providing a substrate having isolation regions formed into a conductive silicon substrate with an oxide layer formed thereon;
- forming a polysilicon layer on the oxide layer;
- forming a trench isolation material over the polysilicon layer;
- forming a patterned photoresist having an opening therein over the trench isolation material;
- etching a trench into the trench isolation material through the opening and exposing a portion of the underlying polysilicon layer;
- growing epitaxial silicon into the bottom of the trench on the exposed portion of the underlying polysilicon layer;
- depositing a metal layer along the sidewalls of the trench and on the epitaxial silicon;
- performing a first anneal on the semiconductor assembly to cause the metal layer to react with the epitaxial silicon to form metal silicide;
- removing any un-reacted metal layer;
- performing a second anneal step to continue the formation of metal silicide;
- depositing an isolation capping material into the trench and over the metal silicide;
- removing the lateral component of the isolation capping material;
- etching selectively to the isolation capping material to form a transistor gate stack comprising a transistor isolation cap, the metal silicide, a portion of the silicon layer and the transistor gate oxide;
- implanting conductive dopants into the conductive silicon substrate to form self-aligned lightly doped source/drain regions of the transistor;
- forming transistor gate sidewall isolation spacers;
- and
- implanting conductive dopants into the conductive silicon substrate to form source/drain regions of the transistor.
14 more elements
A method of forming a transistor gate for a field effect transistor comprising:
- providing a substrate having isolation regions formed into a conductive silicon substrate with an oxide layer formed thereon;
- forming a polysilicon layer on the oxide layer;
- forming a trench isolation material over the polysilicon layer;
- forming a patterned photoresist having an opening therein over the trench isolation material;
- etching a trench into the trench isolation material through the opening to form trench sidewalls in the trench isolation material and to expose a portion of the underlying polysilicon layer;
- growing epitaxial silicon having a thickness of approximately 400-500 Angstroms into the bottom of the trench and on the exposed portion of the underlying polysilicon layer;
- depositing a cobalt layer along the sidewalls of the trench and on the epitaxial silicon;
- depositing a titanium layer on the cobalt layer;
- performing a first anneal on the semiconductor assembly at a temperature range of approximately 500-600° C., for approximately 30 to 60 to cause the metal layer to react with the epitaxial silicon to form cobalt silicide;
- removing of any un-reacted metal layer and cobalt layer;
- performing a second anneal by subjecting the semiconductor assembly to a rapid thermal processing step at a temperature range of approximately 800-900° C. for approximately 30 to 60 seconds to further the formation of cobalt silicide such that the cobalt silicide is approximately 100-350 Angstroms in thickness but does not encroach the portion of the underlying polysilicon layer;
- depositing an isolation capping material into the trench and over the cobalt silicide;
- etching selectively to remove the lateral component of the isolation capping material;
- etching selectively to the isolation capping material to form a transistor gate stack comprising a transistor isolation cap, the cobalt silicide, a portion of the polysilicon layer and the transistor gate oxide;
- implanting conductive dopants to form self-aligned lightly doped source/drain regions of the transistor;
- forming transistor gate sidewall isolation spacers;
- and
- implanting conductive dopants to form source/drain regions of the transistor.
15 more elements
Dependencies are inferred from the claim text.