Method and structure of an auxiliary transistor arrangement used for fabricating a semiconductor memory device
AssigneeInfineon Technologies AG
InventorMichael Sommer
Life of this patent
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Abstract
Method for fabricating a semiconductor memory device having auxiliary transistor structures which are required for lithography and etching processes. A protective structure for reducing leakage currents between gate conductor and doped zone is provided. The protective structure is formed as a region doped oppositely to the doped zone.
Claims17
A method for fabricating a semiconductor memory device that includes auxiliary transistor structures that aid a lithography step, comprising:
- providing a zone for the auxiliary transistor structures that adjoins a section of a substrate surface and is doped with a dopant of a first conduction type;
- providing a gate oxide over a portion of the section;
- and
- providing a conductive layer formed as a gate conductor essentially on the gate oxide, wherein a protective structure for preventing a leakage current path from arising between gate conductor and doped zone is formed in the doped zone.
An auxiliary transistor structure in a semiconductor substrate, comprising:
- a doped zone that adjoins a section of the substrate surface and is doped with a dopant of a first conduction type;
- a gate oxide provided over a portion of the section of the substrate surface;
- and
- a conductive layer that is essentially provided on the gate oxide and is formed as a gate conductor,
- wherein a protective structure for preventing a leakage current path from arising between the gate conductor and doped zone is formed in the doped zone.
A method for fabricating a semiconductor memory device having an auxiliary transistor structure that aids a lithography step, comprising:
- doping a zone adjoining a section of the substrate surface with a dopant of a first conduction type;
- applying a gate oxide over a portion of the section;
- applying a conductive layer serving as gate conductor essentially on the gate oxide;
- and
- implanting a protective structure that extends between two isolation trenches and adjoins the latter, wherein the protective structure serves to prevent a leakage current path from arising between gate conductor and doped zone.
The method of claim 14, wherein the auxiliary transistor structure is introduced into a semiconductor substrate for the purpose of compensating for topology differences.
An auxiliary transistor structure in a semiconductor substrate, comprising:
- a doped zone that adjoins a section of the substrate surface and is doped with a dopant of a first conduction type;
- a gate oxide provided over a portion of the section) of the substrate surface;
- a conductive layer that is essentially provided on the gate oxide and is formed as a gate conductor;
- and
- a protective structure formed in the doped zone and extending between two isolation trenches and adjoining the latter.
Dependencies are inferred from the claim text.