Method for manufacturing a programmable eraseless memory

A method for manufacturing an integrated circuit on a substrate, comprising:

• forming a first plurality of conductive lines on said substrate, said first plurality of conductive lines extending generally in parallel in a first direction;
• forming a second plurality of conductive lines over said first plurality of conductive lines, said second plurality of conductive lines extending generally in parallel in a second direction orthogonal to the first direction defining an array of intersections;
• and
• forming an inter-electrode layer of material at said intersections between said first plurality of conductive lines and said second plurality of conductive lines, said inter-electrode layer of material characterized by progressive change in a property in response to stress, to form memory cells at said intersections;
• and
• providing circuitry on said substrate for applying said stress and sensing said property in said memory cells, wherein the circuitry to apply said stress includes circuits to apply a positive program voltage to a first selected line in the second plurality of conductive lines and a negative program voltage to a second selected line in the first plurality of conductive lines for a time interval, wherein said positive and negative program voltages have respective absolute values less than two volts.

A method for manufacturing an integrated circuit on a substrate, comprising:

• forming a first plurality of conductive lines on said substrate, said first plurality of conductive lines extending generally in parallel in a first direction;
• forming a second plurality of conductive lines over said first plurality of conductive lines, said second plurality of conductive lines extending generally in parallel in a second direction orthogonal to the first direction defining an array of intersections;
• and
• forming an inter-electrode layer of material at said intersections between said first plurality of conductive lines and said second plurality of conductive lines, said inter-electrode layer of material characterized by progressive change in a property in response to stress, to form memory cells at said intersections;
• and
• providing circuitry on said substrate for applying said stress and sensing said property in said memory cells, wherein the circuitry to sense said property includes circuits to apply a read voltage of less than 2 volts across selected ones of the first and second pluralities of conductive lines accessing selected memory cells in the array, and to sense the amount of progressive breakdown.

A method for manufacturing a memory cell, comprising:

• forming a first electrode;
• forming an inter-electrode layer of material on the first electrode, the inter-electrode layer of material having an property characterized by progressive change in response to stress;
• and
• forming a second electrode over the inter-electrode layer of material on the first electrode, wherein said stress comprises voltage less than 5 volts across the first and second electrodes.

A method for manufacturing a memory cell, comprising:

• forming a first electrode;
• forming an inter-electrode layer of material on the first electrode, the inter-electrode layer of material having an property characterized by progressive change in response to stress;
• and
• forming a second electrode over the inter-electrode layer of material on the first electrode, wherein said stress is induced by a positive program voltage on the first electrode and a negative program voltage on the second electrode for a time interval, wherein said positive and negative program voltages have respective absolute values less than two volts.

A method for forming memory cell on a semiconductor substrate, comprising:

• implanting dopant in said semiconductor substrate to form a conductive diffusion region having a first conductivity type;
• forming an inter-electrode layer of material on the conductive diffusion region, the inter-electrode layer of material characterized by progressive change in resistance in response to stress induced by voltage across the layer of less than five volts;
• and
• forming a layer of doped semiconductor having a second conductivity type over said inter-electrode layer of material.

A method for forming memory cell on a silicon substrate, comprising:

• implanting dopant in said silicon substrate to form a conductive diffusion region having a first conductivity type;
• forming a layer of silicon oxide on the conductive diffusion region, the layer of silicon oxide having thickness of less than 15 Angstroms;
• and
• forming a layer of doped polysilicon having a second conductivity type over said layer of silicon oxide.