Crystalline or amorphous medium-K gate oxides, Y2O3 and Gd2O3

A transistor, comprising:

• a first and second source/drain region;
• a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0.6 nm;
• a gadolinium oxide dielectric layer coupled to the surface portion of the body region;
• and
• a gate coupled to the gadolinium oxide dielectric layer.

A memory array, comprising:

• a number of access transistors, including:
• a first and second source/drain region;
• a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0.6 nm;
• a yttrium oxide dielectric layer coupled to the surface portion of the body region;
• a gate coupled to the yttrium oxide dielectric layer;
• a number of wordlines coupled to a number of the gates of the number of access transistors;
• a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors;
• and
• a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors.

A memory array, comprising:

• a number of access transistors, including:
• a first and second source/drain region;
• a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0.6 nm;
• a gadolinium oxide dielectric layer coupled to the surface portion of the body region;
• a gate coupled to the gadolinium oxide dielectric layer;
• a number of wordlines coupled to a number of the gates of the number of access transistors;
• a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors;
• and
• a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors.

An information handling device, comprising:

• a processor;
• a memory array, comprising:
• a number of access transistors, comprising:
• a first and second source/drain region;
• a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0.6 nm;
• a yttrium oxide dielectric layer coupled to the surface portion of the body region;
• a gate coupled to the yttrium oxide dielectric layer;
• a number of wordlines coupled to a number of the gates of the number of access transistors;
• a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors;
• a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors;
• and
• a system bus coupling the processor to the memory device.

An information handling device, comprising:

• a processor;
• a memory array, comprising:
• a number of access transistors, comprising:
• a first and second source/drain region;
• a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0.6 mn;
• a gadolinium oxide dielectric layer coupled to the surface portion of the body region;
• a gate coupled to the gadolinium oxide dielectric layer;
• a number of wordlines coupled to a number of the gates of the number of access transistors;
• a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors;
• a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors;
• and
• a system bus coupling the processor to the memory device.